| 0x280 |
RO |
PHY_STATUS. Provides the current status from the
PHY.
- [1:0] – Reset done for lanes 0 and 1.
- [3:2] – Reset done for lanes 2 and 3.
- [4] – PLL for lanes 0 and 1 locked.
- [5] – PLL for lanes 2 and 3 locked.
- [6] – FPGA fabric clock PLL locked.
- [15:7] – Unused, read as 0.
- [17:16] – Transmitter buffer status, lane 0.
- [19:18] – Unused, read as 0.
- [21:20] – Transmitter buffer status, lane 1.
- [23:22] – Unused, read as 0.
- [25:24] – Transmitter buffer status, lane 2.
- [27:26] – Unused, read as 0.
- [29:28] – Transmitter buffer status, lane 3.
- [31:30] – Unused, read as 0.
|
| 0x4FC |
RO |
SINK_VID_FRAMING_ERROR_STATUS: Sink Video Framing
error status. This is a debug register that is valid when GT data width is
32-bit.
- [1:0] – Stream1 error status in framing.
- [9:8] – Stream2 error status in framing.
- [17:16] – Stream3 error status in framing.
- [25:24] – Stream4 error status in framing.
|