Main Link Setup and Management - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)

Document ID
PG199
Release Date
2024-12-11
Version
2.1 English

This section is intended to elaborate on and act as a companion to the link training procedure as described in section 3.5.1.3 of the VESA® DisplayPort Standard v1.2a.

AMD advises all users of the Source core to use a MicroBlaze™ processor or similar embedded processor to properly initialize and maintain the link. The tasks encompassed in the Link and Stream Policy Makers are unlikely to be efficiently managed by a hardware-based state machine. AMD does not recommend using the RTL-based controllers.

Figure 1. Source Main Link Datapath