MST Interface - 2.1 English

Table 1. MST Interface
Offset	R/W	Definition
0x500	RW	MAIN_STREAM_HTOTAL_STREAM2. Specifies the total number of clocks in the horizontal framing period for the main stream video signal. [15:0] – Horizontal line length total in clocks.
0x504	RW	MAIN_STREAM_VTOTAL_STREAM2. Provides the total number of lines in the main stream video frame. [15:0] – Total number of lines per video frame.
0x508	RW	MAIN_STREAM_POLARITY_STREAM2. Provides the polarity values for the video sync signals. [1] – VSYNC_POLARITY: Polarity of the vertical sync pulse. [0] – HSYNC_POLARITY: Polarity of the horizontal sync pulse.
0x50C	RW	MAIN_STREAM_HSWIDTH_STREAM2. Sets the width of the horizontal sync pulse. [14:0] – Horizontal sync width in clock cycles.
0x510	RW	MAIN_STREAM_VSWIDTH_STREAM2. Sets the width of the vertical sync pulse. [14:0] – Width of the vertical sync in lines.
0x514	RW	MAIN_STREAM_HRES_STREAM2. Horizontal resolution of the main stream video source. [15:0] – Number of active pixels per line of the main stream video.
0x518	RW	MAIN_STREAM_VRES_STREAM2. Vertical resolution of the main stream video source. [15:0] – Number of active lines of video in the main stream video source.
0x51C	RW	MAIN_STREAM_HSTART_STREAM2. Number of clocks between the leading edge of the horizontal sync and the start of active data. [15:0] – Horizontal start clock count.
0x520	RW	MAIN_STREAM_VSTART_STREAM2. Number of lines between the leading edge of the vertical sync and the first line of active data. [15:0] – Vertical start line count.
0x524	RW	MAIN_STREAM_MISC0_STREAM2. Miscellaneous stream attributes. [7:0] – Implements the attribute information contained in the DisplayPort MISC0 register described in section 2.2.4 of the standard. [0] – Synchronous Clock. [2:1] – Component Format. [3] – Dynamic Range. [4] – YCbCr Colorimetry. [7:5] – Bit depth per color/component.
0x528	RW	MAIN_STREAM_MISC1_STREAM2. Miscellaneous stream attributes. [7:0] – Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard. [0] – Interlaced vertical total even. [2:1] – Stereo video attribute. [6:3] – Reserved.
0x52C	RW	M-VID_STREAM2. If synchronous clocking mode is used, this register must be written with the M value as described in section 2.2.5.2 of the standard. When in asynchronous clocking mode, the M value for the video stream as automatically computed by the source core and written to the main stream. These values are not written into the M-VID register for readback. [23:0] – Unsigned M value.
0x530	RW	TRANSFER_UNIT_SIZE_STREAM2. Sets the size of a transfer unit in the framing logic On reset, transfer size is set to 64. [6:0] – This number should be in the range of 32 to 64 and is set to a fixed value that depends on the inbound video mode. Note that bit 0 cannot be written (the transfer unit size is always even).
0x534	RW	N-VID_STREAM2. If synchronous clocking mode is used, this register must be written with the N value as described in section 2.2.5.2 of the standard. When in asynchronous clocking mode, the M value for the video stream as automatically computed by the source core and written to the main stream. These values are not written into the N-VID register for readback. [23:0] – Unsigned N value.
0x538	RW	USER_PIXEL_WIDTH_STREAM2. Selects the width of the user data input port. Use quad pixel mode in MST. [2:0]: 1 = Single pixel wide interface 2 = Dual pixel wide interface 4 = Quad pixel wide interface
0x53C	RW	USER_DATA_COUNT_PER_LANE_STREAM2. This register is used to translate the number of pixels per line to the native internal datapath. If (HRES × bits per pixel) is divisible by 16, then words_per_line = ((HRES x bits per pixel)/16) Else words_per_line = (INT((HRES × bits per pixel)/16)) + 1 For single-lane design: Set USER_DATA_COUNT_PER_LANE = words_per_line - 1 For 2-lane design: If words_per_line is divisible by 2, then Set USER_DATA_COUNT_PER_LANE = words_per_line - 2 Else Set USER_DATA_COUNT_PER_LANE = words_per_line + MOD(words_per_line,2) - 2 For 4-lane design: If words_per_line is divisible by 4, then Set USER_DATA_COUNT_PER_LANE = words_per_line - 4 Else Set USER_DATA_COUNT_PER_LANE = words_per_line + MOD(words_per_line,4) - 4
0x540	RW	MAIN_STREAM_INTERLACED_STREAM2. Informs the DisplayPort transmitter main link that the source video is interlaced. By setting this bit to a '1', the core will set the appropriate fields in the VBID value and Main Stream Attributes. This bit must be set to 1 for the proper transmission of interlaced sources. [0] – Set to 1 when transmitting interlaced images.
0x544	RW	MIN_BYTES_PER_TU_STREAM2: Programs source to use MIN number of bytes per transfer unit. The calculation should be done based on the DisplayPort Standard. [7:0] – Set the value to INT((LINK_BW/VIDEO_BW) x TRANSFER_UNIT_SIZE)
0x548	RW	FRAC_BYTES_PER_TU_STREAM2: Calculating MIN bytes per TU will often not be a whole number. This register is used to hold the fractional component. [9:0] – The fraction part of ((LINK_BW/VIDEO_BW) x TRANSFER_UNIT_SIZE) scaled by 1000 is programmed in this register.
0x54C	RW	INIT_WAIT_STREAM2: This register defines the number of initial wait cycles at the start of a new line by the Framing logic. This allows enough data to be buffered in the input FIFO. If (MIN_BYTES_PER_TU ≤ 4) [7:0] – Set INIT_WAIT to 64 else if color format is RGB/YCbCr_444 [7:0] – Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU) else if color format is YCbCr_422 [7:0] – Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)/2 else if color format is Y_Only [7:0] – Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)/3
0x550	RW	MAIN_STREAM_HTOTAL_STREAM3. Specifies the total number of clocks in the horizontal framing period for the main stream video signal. [15:0] – Horizontal line length total in clocks.
0x554	RW	MAIN_STREAM_VTOTAL_STREAM3. Provides the total number of lines in the main stream video frame. [15:0] – Total number of lines per video frame.
0x558	RW	MAIN_STREAM_POLARITY_STREAM3. Provides the polarity values for the video sync signals. [1] – VSYNC_POLARITY: Polarity of the vertical sync pulse. [0] – HSYNC_POLARITY: Polarity of the horizontal sync pulse.
0x55C	RW	MAIN_STREAM_HSWIDTH_STREAM3. Sets the width of the horizontal sync pulse. [14:0] – Horizontal sync width in clock cycles.
0x560	RW	MAIN_STREAM_VSWIDTH_STREAM3. Sets the width of the vertical sync pulse. [14:0] – Width of the vertical sync in lines.
0x564	RW	MAIN_STREAM_HRES_STREAM3. Horizontal resolution of the main stream video source. [15:0] – Number of active pixels per line of the main stream video.
0x568	RW	MAIN_STREAM_VRES_STREAM3. Vertical resolution of the main stream video source. [15:0] – Number of active lines of video in the main stream video source.
0x56C	RW	MAIN_STREAM_HSTART_STREAM3. Number of clocks between the leading edge of the horizontal sync and the start of active data. [15:0] – Horizontal start clock count.
0x570	RW	MAIN_STREAM_VSTART_STREAM3. Number of lines between the leading edge of the vertical sync and the first line of active data. [15:0] – Vertical start line count.
0x574	RW	MAIN_STREAM_MISC0_STREAM3. Miscellaneous stream attributes. [7:0] – Implements the attribute information contained in the DisplayPort MISC0 register described in section 2.2.4 of the standard. [0] – Synchronous Clock. [2:1] – Component Format. [3] – Dynamic Range. [4] – YCbCr Colorimetry. [7:5] – Bit depth per color/component.
0x578	RW	MAIN_STREAM_MISC1_STREAM3. Miscellaneous stream attributes. [7:0] – Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard. [0] – Interlaced vertical total even. [2:1] – Stereo video attribute. [6:3] – Reserved.
0x57C	RW	M-VID_STREAM3. If synchronous clocking mode is used, this register must be written with the M value as described in section 2.2.5.2 of the standard. When in asynchronous clocking mode, the M value for the video stream as automatically computed by the source core and written to the main stream. These values are not written into the M-VID register for readback. [23:0] – Unsigned M value
0x580	RW	TRANSFER_UNIT_SIZE_STREAM3. Sets the size of a transfer unit in the framing logic On reset, transfer size is set to 64. [6:0] – This number should be in the range of 32 to 64 and is set to a fixed value that depends on the inbound video mode. Note that bit 0 cannot be written (the transfer unit size is always even).
0x584	RW	N-VID_STREAM3. If synchronous clocking mode is used, this register must be written with the N value as described in section 2.2.5.2 of the standard. When in asynchronous clocking mode, the M value for the video stream as automatically computed by the source core and written to the main stream. These values are not written into the N-VID register for readback. [23:0] – Unsigned N value
0x588	RW	USER_PIXEL_WIDTH_STREAM3. Selects the width of the user data input port. Use quad pixel mode in MST. [2:0]: 1 = Single pixel wide interface 2 = Dual pixel wide interface 4 = Quad pixel wide interface
0x58C	RW	USER_DATA_COUNT_PER_LANE_STREAM3. This register is used to translate the number of pixels per line to the native internal 16-bit datapath. If (HRES x bits per pixel) is divisible by 16, then words_per_line = ((HRES × bits per pixel)/16) Else words_per_line = (INT((HRES × bits per pixel)/16)) + 1 For single-lane design: Set USER_DATA_COUNT_PER_LANE = words_per_line - 1 For 2-lane design: If words_per_line is divisible by 2, then Set USER_DATA_COUNT_PER_LANE = words_per_line - 2 Else Set USER_DATA_COUNT_PER_LANE = words_per_line + MOD(words_per_line,2) - 2 For 4-lane design: If words_per_line is divisible by 4, then Set USER_DATA_COUNT_PER_LANE = words_per_line - 4 Else Set USER_DATA_COUNT_PER_LANE = words_per_line + MOD(words_per_line,4) - 4
0x590	RW	MAIN_STREAM_INTERLACED_STREAM3. Informs the DisplayPort transmitter main link that the source video is interlaced. By setting this bit to a 1, the core will set the appropriate fields in the VBID value and Main Stream Attributes. This bit must be set to 1 for the proper transmission of interlaced sources. [0] – Set to 1 when transmitting interlaced images.
0x594	RW	MIN_BYTES_PER_TU_STREAM3: Programs source to use MIN number of bytes per transfer unit. The calculation should be done based on the DisplayPort Standard. [7:0] – Set the value to INT((LINK_BW/VIDEO_BW) x TRANSFER_UNIT_SIZE)
0x598	RW	FRAC_BYTES_PER_TU_STREAM3: Calculating MIN bytes per TU is often not a whole number. This register is used to hold the fractional component. [9:0] – The fraction part of ((LINK_BW/VIDEO_BW) × TRANSFER_UNIT_SIZE) scaled by 1000 is programmed in this register.
0x59C	RW	INIT_WAIT_STREAM3: This register defines the number of initial wait cycles at the start of a new line by the Framing logic. This allows enough data to be buffered in the input FIFO. If (MIN_BYTES_PER_TU ≤ 4) [7:0] – Set INIT_WAIT to 64 else if color format is RGB/YCbCr_444 [7:0] – Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU) else if color format is YCbCr_422 [7:0] – Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)/2 else if color format is Y_Only [7:0] – Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)/3
0x5A0	RW	MAIN_STREAM_HTOTAL_STREAM4. Specifies the total number of clocks in the horizontal framing period for the main stream video signal. [15:0] – Horizontal line length total in clocks.
0x5A4	RW	MAIN_STREAM_VTOTAL_STREAM4. Provides the total number of lines in the main stream video frame. [15:0] – Total number of lines per video frame.
0x5A8	RW	MAIN_STREAM_POLARITY_STREAM4. Provides the polarity values for the video sync signals. [1] – VSYNC_POLARITY: Polarity of the vertical sync pulse. [0] – HSYNC_POLARITY: Polarity of the horizontal sync pulse.
0x5AC	RW	MAIN_STREAM_HSWIDTH_STREAM4. Sets the width of the horizontal sync pulse. [14:0] – Horizontal sync width in clock cycles.
0x5B0	RW	MAIN_STREAM_VSWIDTH_STREAM4. Sets the width of the vertical sync pulse. [14:0] – Width of the vertical sync in lines.
0x5B4	RW	MAIN_STREAM_HRES_STREAM4. Horizontal resolution of the main stream video source. [15:0] – Number of active pixels per line of the main stream video.
0x5B8	RW	MAIN_STREAM_VRES_STREAM4. Vertical resolution of the main stream video source. [15:0] – Number of active lines of video in the main stream video source.
0x5BC	RW	MAIN_STREAM_HSTART_STREAM4. Number of clocks between the leading edge of the horizontal sync and the start of active data. [15:0] – Horizontal start clock count.
0x5C0	RW	MAIN_STREAM_VSTART_STREAM4. Number of lines between the leading edge of the vertical sync and the first line of active data. [15:0] – Vertical start line count.
0x5C4	RW	MAIN_STREAM_MISC0_STREAM4. Miscellaneous stream attributes. [7:0] – Implements the attribute information contained in the DisplayPort MISC0 register described in section 2.2.4 of the standard. [0] – Synchronous Clock. [2:1] – Component Format. [3] – Dynamic Range. [4] – YCbCr Colorimetry. [7:5] – Bit depth per color/component.
0x5C8	RW	MAIN_STREAM_MISC1_STREAM4. Miscellaneous stream attributes. [7:0] – Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard. [0] – Interlaced vertical total even. [2:1] – Stereo video attribute. [6:3] – Reserved.
0x5CC	RW	M-VID_STREAM4. If synchronous clocking mode is used, this register must be written with the M value as described in section 2.2.5.2 of the standard. When in asynchronous clocking mode, the M value for the video stream as automatically computed by the source core and written to the main stream. These values are not written into the M-VID register for readback. [23:0] – Unsigned M value.
0x5D0	RW	TRANSFER_UNIT_SIZE_STREAM4. Sets the size of a transfer unit in the framing logic On reset, transfer size is set to 64. [6:0] – This number should be in the range of 32 to 64 and is set to a fixed value that depends on the inbound video mode. Note that bit 0 cannot be written (the transfer unit size is always even).
0x5D4	RW	N-VID_STREAM4. If synchronous clocking mode is used, this register must be written with the N value as described in section 2.2.5.2 of the standard. When in asynchronous clocking mode, the M value for the video stream as automatically computed by the source core and written to the main stream. These values are not written into the N-VID register for readback. [23:0] – Unsigned N value.
0x5D8	RW	USER_PIXEL_WIDTH_STREAM4. Selects the width of the user data input port. Use quad pixel mode in MST. [2:0]: 1 = Single pixel wide interface 2 = Dual pixel wide interface 4 = Quad pixel wide interface
0x5DC	RW	USER_DATA_COUNT_PER_LANE_STREAM4. This register is used to translate the number of pixels per line to the native internal 16-bit datapath. If (HRES × bits per pixel) is divisible by 16, then words_per_line = ((HRES × bits per pixel)/16) Else words_per_line = (INT((HRES × bits per pixel)/16)) + 1 For single-lane design: Set USER_DATA_COUNT_PER_LANE = words_per_line - 1 For 2-lane design: If words_per_line is divisible by 2, then Set USER_DATA_COUNT_PER_LANE = words_per_line - 2 Else Set USER_DATA_COUNT_PER_LANE = words_per_line + MOD(words_per_line,2) - 2 For 4-lane design: If words_per_line is divisible by 4, then Set USER_DATA_COUNT_PER_LANE = words_per_line - 4 Else Set USER_DATA_COUNT_PER_LANE = words_per_line + MOD(words_per_line,4) - 4
0x5E0	RW	MAIN_STREAM_INTERLACED_STREAM4. Informs the DisplayPort transmitter main link that the source video is interlaced. By setting this bit to a 1, the core sets the appropriate fields in the VBID value and Main Stream Attributes. This bit must be set to 1 for the proper transmission of interlaced sources. [0] – Set to 1 when transmitting interlaced images.
0x5E4	RW	MIN_BYTES_PER_TU_STREAM4. Programs source to use MIN number of bytes per transfer unit. The calculation should be done based on the DisplayPort Standard. [7:0] – Set the value to INT((LINK_BW/VIDEO_BW) x TRANSFER_UNIT_SIZE)
0x5E8	RW	FRAC_BYTES_PER_TU_STREAM4. Calculating MIN bytes per TU is often not a whole number. This register is used to hold the fractional component. [9:0] – The fraction part of ((LINK_BW/VIDEO_BW) × TRANSFER_UNIT_SIZE) scaled by 1000 is programmed in this register.
0x5EC	RW	INIT_WAIT_STREAM4. This register defines the number of initial wait cycles at the start of a new line by the Framing logic. This allows enough data to be buffered in the input FIFO. If (MIN_BYTES_PER_TU ≤ 4): [7:0] – Set INIT_WAIT to 64 else if color format is RGB/YCbCr_444 [7:0] – Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU) else if color format is YCbCr_422 [7:0] – Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)/2 else if color format is Y_Only [7:0] – Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)/3
0x800 to 0x8FF	WO	PAYLOAD_TABLE. This address space maps to the VC payload table that is maintained in the core. [7:0] – Payload data

MST Interface - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)