Link Configuration Field - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)
Document ID
PG199
Release Date
2024-12-11
Version
2.1 English
Table 1. Link Configuration Field
Offset R/W Definition
0x000 RW

LINK_BW_SET. Main link bandwidth setting. The register uses the same values as those supported by the DPCD register of the same name in the sink device.

  • [7:0] – LINK_BW_SET: Sets the value of the main link bandwidth for the sink device.
  • 0x06 = 1.62 Gb/s
  • 0x0A = 2.7 Gb/s
  • 0x14 = 5.4 Gb/s
0x004 RW

LANE_COUNT_SET. Sets the number of lanes used by the source in transmitting data.

  • [4:0] – Set to 1, 2, or 4
0x008 RW

ENHANCED_FRAME_EN

  • [0] –Set to 1 by the source to enable the enhanced framing symbol sequence.
0x00C RW

TRAINING_PATTERN_SET. Sets the link training mode.

  • [1:0] – Set the link training pattern according to the two bit code.
  • 00 = Training off
  • 01 = Training pattern 1, used for clock recovery
  • 10 = Training pattern 2, used for channel equalization
  • 11 = Training pattern 3, used for channel equalization for cores with DisplayPort Standard v1.2a.
0x010 RW

LINK_QUAL_PATTERN_SET. Transmit the link quality pattern.

  • [2:0] – Enable transmission of the link quality test patterns.
  • 000 = Link quality test pattern not transmitted
  • 001 = D10.2 test pattern (unscrambled) transmitted
  • 010 = Symbol Error Rate measurement pattern
  • 011 = PRBS7 transmitted
  • 100 = Custom 80-bit pattern
  • 101 = HBR2 compliance pattern
0x014 RW

SCRAMBLING_DISABLE. Set to 1 when the transmitter has disabled the scrambler and transmits all symbols.

  • [0] – Disable scrambling.
0x01C WO

SOFTWARE_RESET. Reads will return zeros.

  • [0] – Soft Video Reset: When set, video logic is reset (stream 1).
  • [1] – Soft Video Reset: When set, video logic is reset (stream 2).
  • [2] – Soft Video Reset: When set, video logic is reset (stream 3).
  • [3] – Soft Video Reset: When set, video logic is reset (stream 4).
  • [7] – AUX Soft Reset. When set, AUX logic is reset.
0x020 RW Custom 80-bit quality pattern Bits[31:0]
0x024 RW Custom 80-bit quality pattern Bits[63:32]
0x028 RW

[15:0] – Custom 80-bit quality pattern Bits[79:64]

[31:16] – Reserved