The core supports a special AUX channel command intended to make I2C over AUX transactions faster and easier to perform. In this case, the host will bypass the external I2C master/slave interface and initiate the command by directly writing to the register set.
The sequence for performing these transactions is exactly the same as a native AUX channel transaction with a change to the command written to the AUX_COMMAND register. The supported I2C commands are summarized in the following table.
| AUX_COMMAND[11:8] | Command |
|---|---|
| 0x0 | IIC Write |
| 0x4 | IIC Write MOT |
| 0x1 | IIC Read |
| 0x5 | IIC Read MOT |
| 0x6 | IIC Write Status with MOT |
| 0x2 | IIC Write Status |
By using a combination of these commands, the host can emulate an I2C transaction.
The following figure shows the flow of commanded I2C transactions.
Because I2C transactions might be significantly slower than AUX channel transactions, the host should be prepared to receive multiple AUX_DEFER reply codes during the execution of the above state machines.
The AUX-I2C commands are as follows:
- MOT Definition:
- Middle Of Transaction bit in the command field.
- This controls the stop condition on the I2C slave.
- For a transaction with MOT set to 1, the I2C bus is not STOPPED, but left to remain the previous state.
- For a transaction with MOT set to 0, the I2C bus is forced to IDLE at the end of the current command or in special Abort cases.
- Partial ACK:
- For I2C write transactions, the Sink core can respond with a partial ACK (ACK response followed by the number of bytes written to I2C slave).
Special AUX commands include:
- Write Address Only and Read Address Only: These commands do
not have any length field transmitted over the AUX channel. The intent of these commands
are to:
- Send address and RD/WR information to I2C slave. No Data is transferred.
- End previously active transaction, either normally or through an abort.
The Address Only Write and Read commands are generated from the source by using bit [12] of the command register with command as I2C WRITE/READ.
- Write Status: This command does not have any length information. The intent of the
command is to identify the number of bytes of data that have been written to an I2C slave
when a Partial ACK or Defer response is received by the source on a AUX-I2C write.
The Write status command is generated from the source by using bit [12] of the command register with command as I2C WRITE STATUS.
- IIC Timeout: The sink controller monitors the IIC bus after a transaction starts and looks for an IIC stop occurrence within 1 second. If an IIC stop is not received, it is considered as an IIC timeout and the sink controller issues a stop condition to release the bus. This timeout avoids a lock-up scenario.
Generation of AUX transactions are described in the following table.
| AUX Transaction | Sequence | |
|---|---|---|
| Write Address only with MOT = 1 | ||
| AUX Transaction | START ->CMD ->ADDRESS ->STOP |
1. Write AUX Address register(0x108) with device address. 2. Issue command to transmit transaction by writing into AUX command register (0x100). Bit[12] must be set to 1. |
| I2C Transaction | START -> DEVICE_ADDR -> WR -> ACK/NACK | |
| Usage | Set up I2C slave for Write to defined address. | |
| Read Address only with MOT = 1 | ||
| AUX Transaction | START -> CMD -> ADDRESS ->STOP |
1. Write AUX Address register with device address. 2. Issue command to transmit transaction by writing into AUX command register. Bit [12] must be set to 1. |
| I2C Transaction | START ->DEVICE_ADDR ->RD -> ACK/NACK | |
| Usage | Set up I2C slave for Read to defined address. | |
| Write / Read Address only with MOT = 0 | ||
| AUX Transaction | START ->ADDRESS ->STOP |
1. Write AUX Address register (0x108) with device address. 2. Issue command to transmit transaction by writing into AUX command register (0x100). Bit[12] must be set to 1. |
| I2C Transaction | STOP | |
| Usage | To stop the I2C slave, used as Abort or normal stop. | |
| Write with MOT = 1 | ||
| AUX Transaction | START -> CMD -> ADDRESS -> LENGTH -> D0 to DN -> STOP |
1. Write AUX Address register (0x108) with device address. 2. Write the data to be transmitted into AUX write FIFO register (0x104). 3. Issue write command and data length to transmit transaction by writing into AUX command register (0x100). Bits[3:0] represent length field. |
| I2C Transaction |
I2C bus is IDLE or New device address START -> START/RS -> DEVICE_ADDR -> WR -> ACK/NACK -> DATA0 -> ACK/NACK to DATAN -> ACK/NACK I2C bus is in Write state and the same device address DATA0 -> ACK/NACK to DATAN -> ACK/NACK |
|
| Usage | Set up I2C slave write data. | |
| Write with MOT = 0 | ||
| AUX Transaction |
START ->CMD ->ADDRESS -> LENGTH -> D0 to DN ->STOP |
1. Write AUX Address register (0x108) with device address. 2. Write the data to be transmitted into AUX write FIFO register (0x104). 3. Issue write command and data length to transmit transaction by writing into AUX command register (0x100). Bits[3:0] represent length field. |
| I2C Transaction |
I2C bus is IDLE or Different I2C device address START -> START/RS -> DEVICE_ADDR ->WR -> ACK/NACK ->DATA0 -> ACK/NACK to DATAN ->ACK/NACK -> STOP I2C bus is in Write state and the same I2C device address DATA0 ->ACK/NACK to DATAN -> ACK/NACK -> STOP |
|
| Usage | Set up I2C slave write data and stop the I2C bus after the current transaction. | |
| Read with MOT = 1 | ||
| AUX Transaction | START ->CMD ->ADDRESS -> LENGTH ->STOP |
1. Write AUX Address register (0x108) with device address. 2. Issue read command and data length to transmit transaction by writing into AUX command register (0x100). Bits[3:0] represent the length field. |
| I2C Transaction |
I2C bus is IDLE or Different I2C device address START -> START/RS -> DEVICE_ADDR -> RD ->ACK/NACK ->DATA0 -> ACK/NACK to DATAN ->ACK/NACK I2C bus is in Write state and the same I2C device address DATA0 ->ACK/NACK to DATAN -> ACK/NACK |
|
| Usage | Set up I2C slave read data. | |
| Read with MOT = 0 | ||
| AUX Transaction | START -> CMD -> ADDRESS -> LENGTH -> D0 to DN -> STOP |
1. Write AUX Address register (0x108) with device address. 2. Issue read command and data length to transmit transaction by writing into AUX command register (0x100). Bits[3:0] represent the length field. |
| I2C Transaction |
I2C bus is IDLE or Different I2C device address START -> START/RS ->DEVICE_ADDR -> RD -> ACK/NACK ->DATA0 -> ACK/NACK to DATAN -> ACK/NACK ->STOP I2C bus is in Write state and the same I2C device address DATA0 ->ACK/NACK to DATAN -> ACK/NACK ->STOP |
|
| Usage | Set up I2C slave read data and stop the I2C bus after the current transaction. | |
| Write Status with MOT = 1 | ||
| AUX Transaction | START ->CMD ->ADDRESS ->STOP |
1. Write AUX Address register (0x108) with device address. 2. Issue status update command to transmit transaction by writing into AUX command register (0x100). Bit[12] must be set to 1. |
| I2C Transaction | No transaction | |
| Usage | Status of previous write command that was deferred or partially ACKED. | |
| Write Status with MOT = 0 | ||
| AUX Transaction | START ->CMD ->ADDRESS ->STOP |
1. Write AUX Address register (0x108) with device address. 2. Issue status update command to transmit transaction by writing into AUX command register (0x100). Bit[12] must be set to 1. |
| I2C Transaction | Force a STOP and the end of write burst | |
| Usage | Status of previous write command that was deferred or partially ACKED. MOT = 0 ensures that the bus returns to IDLE at the end of the burst. | |
Handling I2C Read Defers/Timeout:
- The Sink core could issue a DEFER response for a burst read
to I2C. The following are the actions that can be taken by the Source core.
- Issue the same command (previously issued read, with same device address and length) and wait for response. The Sink core on completion of the read from I2C (after multiple defers) should respond with read data.
- Abort the current read using:
- Read to a different I2C slave
- Write command
- Address-only Read or write with MOT = 0.
Handling I2C Write Partial ACK:
- The sink could issue a partial ACK response for a burst
Write to I2C. The following are the actions that can be taken by the Source core:
- Use the Write status command to poll the transfers happening to the I2C. On successful completion, the sink should issue a NACK response to these requests while intermediate ones will get a partial ACK.
- Issue the same command for a response (previously issued with the same device address, length and data) and wait for a response. On completion of the write to I2C (after multiple partial ACKs), the Sink core should respond with an ACK.
- Abort the current Write using:
- Write to a different I2C slave
- Read command
- Address-only Read or Write with MOT = 0.
Handling I2C Write Defer/Timeout:
- The Sink core could issue a Defer response for a burst write
to I2C. The following are the actions that can be taken by the Source core:
- Use the Write status command to poll the transfers happening to the I2C. On successful completion, the Sink core should issue an ACK response to these requests while intermediate ones will get partial ACKs.
- Issue the same command (previously issued with the same device address, length and data) and wait for response. The Sink core on completion of the write to I2C (after multiple Defers) should respond with an ACK.
- Abort the current Write using:
- Write to a different I2C slave
- Read command
- Address only Read or Write with MOT = 0.