Example Design - 2.1 English

Example Design - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)

Document ID

PG199

Release Date

2024-12-11

Version

2.1 English

Note: All example designs use the TED DP1.2 FMC Card from inrevium (TB-FMCH-DP3).

This chapter contains step-by-step instructions for generating an Application Example Design from the DisplayPort Subsystem by using the AMD Vivado™ Design Suite flow.

Recommended: For ZCU102 (Revision 1.0 or later), you should set up a 1.8V setting after connecting the DisplayPort FMC. See the Setting the FMC Voltage to 1.8 V section. For more information, see the ZCU102 System Controller – GUI Tutorial (XTP433).

The following table shows the available example designs for DisplayPort TX.

Table 1. Available Example Designs
GT Type	Topology	Video PHY Config		Hardware	GT Data Width	BPC	Processor
GT Type	Topology	(TXPLL)	(RXPLL)	Hardware	GT Data Width	BPC	Processor
GTXE2	Pass-through with HDCP1.3	CPLL	CPLL	KC705 + TED DP1.2 FMC	2-byte	10	MicroBlaze
GTXE2	Pass-through without HDCP1.3	CPLL	CPLL	KC705 + TED DP1.2 FMC	4-byte	10	MicroBlaze
GTHE3	Pass-through without HDCP1.3	QPLL	CPLL	KCU105 + TED DP1.2 FMC	2-byte	10	MicroBlaze
GTHE4	RX only	–	CPLL	ZCU102 + TED DP1.2 FMC	2-byte	10	A53
GTHE4	TX only	QPLL	–	ZCU102 + TED DP1.2 FMC	2-byte	10	A53