Dual Splitter Registers - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)

Document ID: PG199
Release Date: 2024-12-11
Version: 2.1 English

The following table defines the Dual Splitter registers.

Table 1. Dual Splitter Register Definitions
Offset	Register	Access	Default Value	Definition
0x0000	GENR_CONTROL_REG	R/W	0x2	[0] – Enables the splitter. [1] – Register update. [31] – Soft reset bit. Other registers can be programed by writing a value 2 to this register. At the end of programing set the register to 3.
0x0008	GENR_ERROR_REG	R/W	0x0	[0] – Slave EOL early. [1] – Slave EOL late. [2] – Slave SOF early. [3] – Slave SOF late.
0x000C	IRQ_ENABLE	R/W	0	[0] – Interrupt based on the error conditions.
0x0020	TIME_CONTROL REG	R/W	0x0870_0F00	Contains the input image size: [15:0] – Height¹ [31:16] – Width Note: For UHD @60 frame split mode, HRES must be programmed to actual HRES/4.
0x0100	CORE_CONTROL_REG	R/W	0x00_01_01_01	For UHD @ 60 frame split mode, this register can be programmed to 0x020404. For all other modes, it can be 0x10404. [7:0] – Input number of samples per clock. [15:8] – Output number of samples per clock. [23:16] – Number of image segments. [31:24] – Number of samples overlapping the segments. Should be programmed to 0 because the subsystem supports two frames without overlap.
Height refers to VRES and the WIDTH refers to HRES.