Dual Splitter Programming - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)
Document ID
PG199
Release Date
2024-12-11
Version
2.1 English

Use the following steps to program the Dual Splitter.

  1. Write 0x02 in GENR_CONTROL_REG. This begins the programming sequence and the Dual Splitter register update bit is set.
  2. Write vertical resolution and horizontal resolution in TIME_CONTROL_REG.
  3. The Dual Splitter is used in a configuration where the input frame must be split into two vertical halves. Write the overlap, number of segments, output samples per clock and input samples per clock in CORE_CONTROL_REG.

    For 4k frame split mode, write 0x02_04_04 to register 0x100 (number of segments = 2; number of samples per clock at output = 4; number of samples per clock at input = 4).

    For other modes, write 0x010404 (number of segments =1 (bypass); number of output samples = 4; number of input samples = 4).

  4. Write 0x03 in GENR_CONTROL_REG to enable the Dual Splitter for programmed resolutions and splitting functionality.

When programming the Dual Splitter, note the following:

  • There should be no overlap of the two segments in a frame.
  • Segment 0 of the Dual Splitter is the left frame and Segment 1 is the right frame.
  • The timing of two segments of the splitter is independent, but by the start of a new line, both the segments complete the previous line.
  • For UHD @ 60 in frame split mode, the width of the frame (HRES) must be equal to actual HRES/4.