Required Constraints
This section is not applicable for this IP subsystem.
Device, Package, and Speed Grade Selections
See IP Facts for details about supported devices.
Clock Frequencies
See Clocking for more details about clock frequencies. For more information on GT clocking, see the Video PHY Controller LogiCORE IP Product Guide (PG230).
Clock Management
This section is not applicable for this IP subsystem.
Clock Placement
This section is not applicable for this IP subsystem.
Banking
For more information on the specific banking constraints, see the Video PHY Controller LogiCORE IP Product Guide (PG230).
Transceiver Placement
For more information on the specific transceiver placement constraints, see the Video PHY Controller LogiCORE IP Product Guide (PG230).
I/O Standard and Placement
This section contains details about I/O constraints.
AUX Channel
The VESA DisplayPort Standard describes the AUX channel as a bidirectional LVDS signal. For 7 series designs, the core uses IOBUFDS (bidirectional buffer) as the default with the LVDS standard. You should design the board as recommended by the VESA DP Protocol Standard. For reference, see the example design XDC file.
For AMD Kintex™ 7 devices supporting HR IO banks, use the following constraints:
set_property IOSTANDARD LVDS_25 [get_ports aux_tx_io_p]set_property IOSTANDARD LVDS_25 [get_ports aux_tx_io_n]For Sink:
set_property IOSTANDARD LVDS_25 [get_ports aux_rx_io_p]set_property IOSTANDARD LVDS_25 [get_ports aux_rx_io_n]For AMD Kintex™ 7 and Virtex 7 devices supporting HP IO banks, use the following constraints:
For Source:
set_property IOSTANDARD LVDS [get_ports aux_tx_io_p]set_property IOSTANDARD LVDS [get_ports aux_tx_io_n]For Sink:
set_property IOSTANDARD LVDS [get_ports aux_rx_io_p]set_property IOSTANDARD LVDS [get_ports aux_rx_io_n]HPD
The HPD signal can operate in either a 3.3V or 2.5V I/O bank. By definition in the standard, it is a 3.3V signal.
For Kintex 7 devices supporting HR IO banks, use the following constraints:
set_property IOSTANDARD LVCMOS25 [get_ports hpd];For Virtex 7 devices supporting HP IO banks, use the following constraints:
set_property IOSTANDARD LVCMOS18 [get_ports hpd];Board design and connectivity should follow DisplayPort Standard recommendations with proper level shifting.