Clocking - 2.1 English - PG199

This section describes the link clock, tx_lnk_clk, and the video clock, tx_vid_clk_stream1. The AXI4-Stream to Video bridge can handle asynchronous clocking. The value is based on the Consumer Electronics Association (CEA)/VESA Display Monitor Timing (DMT) standard for given video resolutions. Similarly for MST mode, tx_vid_clk_stream<n> and s_axis_aclk_stream<n> can be same or the s_axis_aclk_stream<n> can be at a higher frequency than tx_vid_clk_stream<n>.

The tx_lnk_clk is a link clock input to the DisplayPort TX Subsystem generated by the Video PHY (GT). The frequency of tx_lnk_clk is <line_rate> /40 MHz for the 32-bit video PHY(GT) data interface and <line_rate> /20 MHz for the 16-bit interface. See the following table for the recommended values.

In the 16-bit GT interface, the hdcp_ext_clk input must be driven from an external MMCM where it has a frequency requirement of hdcp_ext_clk = tx_lnk_clk /2 MHz.

In native mode, the TX video clock has to be as per the value based on the CEA/VESA Display Monitor Timing (DMT) standard for given video resolutions.

The core uses six clock domains:

lnk_clk

The txoutclk from the Video PHY is connected to the TX subsystem link clock. Most of the core operates in link clock domain. This domain is based on the lnk_clk_p/n reference clock for the transceivers. The link rate switching is handled by a DRP state machine in the core PHY later. When the lanes are running at 2.7 Gb/s, lnk_clk operates at 135 MHz. When the lanes are running at 1.62 Gb/s, lnk_clk operates at 81 MHz. When the lanes are running at 5.4 Gb/s, lnk_clk operates at 270 MHz.

Note: lnk_clk = link_rate /20, when GT-Data width is 16-bit. lnk_clk = link_rate /40, when GT-Data width is 32-bit.

vid_clk

This is the primary user interface clock. It has been tested to run up to 150 MHz, which accommodates to a screen resolution of 2560x1600 when using two-wide pixels and larger when using the four-wide pixels. Based on the DisplayPort Standard, the video clock can be derived from the link clock using mvid and nvid.

s_axi_aclk

This is the processor domain. It has been tested to run up to 135 MHz. The AUX clock domain is derived from this domain, but requires no additional constraints. In UltraScale FPGA s_axi_aclk clock is connected to a free-running clock input. gtwiz_reset_clk_freerun_in is required by the reset controller helper block to reset the transceiver primitives. A new GUI parameter is added for AXI_Frequency, when the DisplayPort IP is targeted to UltraScale FPGA. The requirement is s_axi_aclk ≤ lnk_clk.

aud_clk

This is the audio interface clock. The frequency will be equal to 512 × audio sample rate.

s_aud_axis_aclk

This clock is used by the source audio streaming interface. This clock should be = 512 × audio sample rate.

m_aud_axis_aclk

This clock is used by the sink audio streaming interface. This clock should be = 512 × audio sample rate.