Address Map Example - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)

Document ID
PG199
Release Date
2024-12-11
Version
2.1 English

The following table shows an example based on a subsystem base address of 0x44C0_0000 (19 bits). The DisplayPort TX Subsystem requires a 19-bit address mapping, starting at an offset address of 0x00000.

This address map example is applicable when TX subsystem is configured in AXI4-Stream Interface mode. In the mode, the Dual Splitter and Video Timing Controller are not present.

Table 1. Address Map Example
  SST MST
DisplayPort TX Core 0x44C0_0000 0x44C0_0000
Dual Splitter N/A 0x44C0_1000
VTC 0 0x44C0_1000 0x44C0_2000
VTC 1 (N = 2) N/A 0x44C0_3000
VTC 2 (N = 3) N/A 0x44C0_4000
VTC 3 (N = 4) N/A 0x44C0_5000
HDCP Controller 0x44C0_2000 N/A
AXI Timer 0x44C0_3000 N/A