AXI4-Lite Interface Ports - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)
Document ID
PG199
Release Date
2024-12-11
Version
2.1 English
Table 1. AXI4-Lite Interface Ports
Signal Name I/O Description
s_axi_aclk I AXI Bus Clock.
s_axi_aresetn I AXI Reset. Active-Low.
s_axi_awaddr[18:0] I Write Address
s_axi_awprot I Protection type.
s_axi_awvalid I Write address valid.
s_axi_awready O Write address ready.
s_axi_wdata[31:0] I Write data bus.
s_axi_wstrb[3:0] I Write strobes.
s_axi_wvalid I Write valid.
s_axi_wready O Write ready.
s_axi_bresp[1:0] O Write response.
s_axi_bvalid O Write response valid.
s_axi_bready I Response ready.
s_axi_araddr[18:0] I Read address.
s_axi_arprot[1:0] I Protection type.
s_axi_arvalid I Read address valid.
s_axi_arready O Read address ready.
s_axi_rdata[31:0] O Read data.
s_axi_rresp[1:0] O Read response.
s_axi_rvalid O Read valid.
s_axi_rready I Read ready.