Using TX Pattern Generator - 4.1 English

Using TX Pattern Generator - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)

Document ID

PG198

Release Date

2025-01-30

Version

4.1 English

In 8B10B mode, the TX pattern generator can be enabled by changing the value of the TXPRBSSEL port to select the desired pattern.

In 64B66B mode, the TX asynchronous gearbox is enabled, and these additional steps must be taken to enable the TX pattern generator.

1.Put the PCS into reset by asserting TXPCSRESET.

2.Set attribute TXGEARBOX_EN to 1'b0 and TXBUF_EN to 1'b1 via DRP.

3.Set port TXOUTCLKSEL to 3'b010 (TXOUTCLKPMA).

4.Set port TXPRBSSEL to the desired pattern.

5.Release the PCS from reset by deasserting TXPCSRESET and wait for TXRESETDONE to assert.

To return to normal operation using the TX asynchronous gearbox, the above changes must be reversed as described below:

1.Put the PCS into reset by asserting TXPCSRESET.

2.Set the attribute TXGEARBOX_EN to 1'b1 and TXBUF_EN to 1'b0 via the DRP.

3.Set port TXOUTCLKSEL to 3'b101 (TXPROGDIVCLK).

4.Set port TXPRBSSEL to 4'b0000.

5.Release the PCS from reset by deasserting TXPCSRESET and wait for TXRESETDONE to assert.

Table 2-63: RXPOLARITY
Bits	Default Value	Description
0	0	The RXPOLARITY port can invert the polarity of incoming data: 0 = Not inverted. RXP +ve and RXN -ve. 1 = Inverted. RXP is -ve and RXN is +ve.

Table 2-64: RXLPMEN
Bits	Default Value	Description
0	1	Select the RX equalizer setting. There are two types of adaptive filtering depending on system level trade-offs between power and performance. Optimized for power with lower channel loss, the receiver has a power-efficient adaptive mode named the low-power mode (LPM). For equalizing lossier channels, the DFE mode is available. 0 = DFE 1 = LPM

Table 2-65: RXDFELPMRESET
Bits	Default Value	Description
0	0	Reset for LPM and DFE datapath. Must be toggled after switching between modes to initialize adaptation.

Table 2-66: RX Invalid SYNC Header Max
Bits	Default Value	Description
3:0	8	Set max number of invalid sync headers before dropping block sync. Valid values are 1-8.