Each instance of the JESD204 PHY core created by the AMD Vivado™ Design Suite is delivered with an example design that can be implemented in an FPGA and simulated. This design can be used as a starting point for your own design or can be used to troubleshoot your application, if necessary.
See Example Design for information about using and customizing the example designs for the JESD204 PHY core. For more information on the Vivado IP integrator, see the JESD204C LogiCORE IP Product Guide (PG242) [Ref 15].