Transmitter Interface Ports - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)
Document ID
PG198
Release Date
2025-01-30
Version
4.1 English

The transmitter interface ports available on the JESD204 PHY core are shown in Table: TX Parallel Data Interface Ports – JESD204C Configuration.

 

 

 

 

Table 2-5:      TX Parallel Data Interface Ports – JESD204C Configuration

Signal Name

I/O

Clock Domain

Description

gtN_txdata[63:0]

I

tx_core_clock

Data from TX core. N = 0 … [Lanes – 1]

gtN_txheader[1:0]

I

tx_core_clock

Header flag from TX core

gtN_txcharisk[3:0]

I

tx_core_clock

Char is K from TX core. N = 0 … [Lanes – 1]
Table 2-6:      TX: Transceiver Serial Interface Ports

Signal Name

I/O

Clock Domain

Description

txp_out[N:0]

O

tx_core_clock

Positive differential serial data output
N = (Lanes – 1)

txn_out[N:0]

O

tx_core_clock

Negative differential serial data output
N = (Lanes – 1)