Transceiver Debug Interface - 4.1 English - PG198

gtN_drpaddr [9:0]

I

drp_clk

DRP Address Bus

Note:   Not present when AXI4-Lite Management Interface is enabled.

Note:   GTH=[8:0], GTY=[9:0]

gtN_drpdi [15:0]

I

drp_clk

Data bus for writing configuration data from the FPGA logic resources to the transceiver.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gtN_drpen

I

drp_clk

DRP Enable Signal

0 = No read or write operation performed
1 = Enables a read or write operation

Note:   Not present when AXI4-Lite Management Interface is enabled.

gtN_drpwe

I

drp_clk

DRP Write Enable

0 = Read operation when DEN is 1
1 = Write operation when DEN is 1

Note:   Not present when AXI4-Lite Management Interface is enabled.

gtN_drpdo [15:0]

O

drp_clk

Data bus for reading configuration data from the transceiver to the device logic resources.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gtN_drprdy

O

drp_clk

Indicates operation is complete for write operations and data is valid for read operations.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_txpmareset [(LANES-1):0]

I

Async

This port is pulsed High to start the TX PMA reset process.

gt_txpcsreset [(LANES-1):0]

I

Async

This port is pulsed High to start the TX PCS reset process.

gt_txresetdone [(LANES-1):0]

O

tx_core_clock

A High on this port indicates that the TX reset process has completed.

gt_rxpmareset [(LANES-1):0]

I

Async

This port is pulsed High to start the RX PMA reset process.

gt_rxpcsreset [(LANES-1):0]

I

Async

This port is pulsed High to start the RX PCS reset process.

gt_rxbufreset [(LANES-1):0]

I

Async

This port is driven High and then deasserted to start the RX elastic buffer reset process.

gt_rxpmaresetdone [(LANES-1):0]

O

Async

A High on this port indicates that the RX PMA reset process has completed.

gt_rxresetdone [(LANES-1):0]

O

rx_core_clock

A High on this port indicates that the RX reset process has completed.

gt_txbufstatus [(LANES*2)-1:0]

O

tx_core_clock

Elastic Buffer Status

gt_rxbufstatus [(LANES*3)-1:0]

O

rx_core_clock

RX Elastic Buffer Status

gt_cplllock [(LANES-1):0]

O

refclk

Active-High signal indicating that the channel PLL has locked to the input reference clock.

gt_rxrate [(LANES*3)-1:0]

I

rx_core_clock

Link signaling rate control

gt_eyescantrigger [(LANES-1):0]

I

rx_core_clock

A High on this port causes an EYESCAN trigger event.

gt_eyescanreset [(LANES-1):0]

I

Async

This port is pulsed High to initiate the EYESCAN reset process.

gt_eyescandataerror [(LANES-1):0]

O

Async

Asserted when an EYESCAN error occurs.

gt_loopback [(LANES*3)-1:0]

I

Async

Transceiver loopback:

•000 = No loopback
001 = Near-end PCS Loopback
010 = Near-end PMA Loopback
100 = Far-end PMA Loopback
110 = Far-end PCS Loopback

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_rxpolarity [(LANES-1):0]

I

rx_core_clock

Set High to invert the incoming serial data.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_txpolarity [(LANES-1):0]

I

tx_core_clock

Set High to invert the outgoing serial data.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_rxdfelpmreset [(LANES-1):0]

I

Async

Reset for the LPM and DFE datapath.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_rxlpmen [(LANES-1):0]

I

Async

Set to 1 to select the LPM datapath.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_txprecursor [(LANES*5)-1:0]

I

tx_core_clock

Transmitter pre-cursor pre-emphasis control.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_txpostcursor [(LANES*5)-1:0]

I

tx_core_clock

Transmitter post-cursor pre-emphasis control.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_txdiffctrl [(LANES*4)-1:0]

I

Async

Driver swing control.

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_txprbsforceerr [(LANES-1):0]

I

tx_core_clock

Set High to drive errors into the PRBS transmitter.

gt_txinhibit

[LANES-1:0]

I

tx_core_clock

TX Inhibit

gt_pcsrsvdin

[(LANES*16)-1:0]

I

Async

16 bits per lane. Bit [2] is DRP reset.

Reading read-only registers while the XCLK is not toggling (e.g., during reset or change of reference clocks), causes the DRP to not return a DRPRDY signal and prevent further DRP transactions. In such an event, PCSRSVDIN[2] must be pulsed to reset the DRP interface before initiating further DRP transactions.

gt_rxprbssel [(LANES*4)-1:0]

I

rx_core_clock

Receiver PRBS checker test pattern control.

gt_rxprbserr [(LANES-1):0]

I

rx_core_clock

A High on this port indicates that PRBS errors have occurred.

gt_rxprbscntreset [(LANES-1):0]

I

rx_core_clock

Reset the PRBS error counter

gt_rxcdrhold [(LANES-1):0]

I

Async

Hold the CDR control loop frozen

gt_dmonitorout [(LANES*15-1):0]

O

Async

Digital Monitor Output Bus

gt_rxdisperr [(LANES*4-1):0]

O

rx_core_clock

Receiver disparity error indicator

gt_rxnotintable [(LANES*4-1):0]

O

rx_core_clock

Receiver not in table error indicator

gt_rxcommadet [(LANES-1):0]

O

rx_core_clock

A High on this port indicates that the comma alignment block has detected a valid comma.

gt_rxpd [(LANES*2-1):0]

I

Async

RX Power Down

00=Normal Operation

11=Lowest power mode

Note:   Not present when AXI4-Lite Management Interface is enabled.

gt_txpd [(LANES*2-1):0]

I

tx_core_clock

TX Power Down

00=Normal Operation

11=Lowest power mode

Note:   Not present when AXI4-Lite Management Interface is enabled.

Notes:

1.N is the number of the transceiver channels.