Transceiver Control - 4.1 English

The following controls are split into three banks internally to minimize the clock domain crossings required for each interface. This does require three separate writes to the select registers. The AXI read/write manages the clock domain crossing, with the result that the AXI accesses are longer than standard.

For accesses to the Transceiver register banks 1 to 3, ensure that register gt_interface_sel (0x024) is programmed with the index of the Transceiver that is required. The range is 0 to M-1, where M is the value returned in the “Number of Transceiver interfaces” register (0x00C).

Table 2-46: RXPD
Bits	Default Value	Description
1:0	0	Power up or down the RX of the GT transceiver. 00 = Power state for normal operation. 11 = Power saving state with lowest power.

Table 2-47: CPLLPD
Bits	Default Value	Description
0	0	1 = Power Down CPLL

Table 2-48: Transmit PLL Clock Select⁽¹⁾
Bits	Default Value	Description
1:0	0	Selects the PLL to drive the TX datapath: 00 = CPLL 10 = QPLL1 11 = QPLL0
Notes: 1.The PHY IP core contains a single Transmit PLL Clock Select register which can be programmed to any index.

Table 2-49: Receive PLL Clock Select⁽¹⁾
Bits	Default Value	Description
1:0	0	Selects the PLL to drive the RX datapath: 00 = CPLL 10 = QPLL1 11 = QPLL0
Notes: 1.The PHY IP core contains a single Receive PLL Clock Select register which can be programmed to any index.

Table 2-50: TX Postcursor
Bits	Default Value	Description
4:0	0	Driver Swing Control. Refer to the relevant transceiver user guide [Ref 10], [Ref 11].

Table 2-51: TX Precursor
Bits	Default Value	Description
4:0	0	Transmitter precursor TX pre-emphasis control. Refer to the relevant transceiver user guide [Ref 10], [Ref 11].

Table 2-52: Loopback
Bits	Default Value	Description
2:0	0	Loopback modes are specialized configurations of the transceiver datapath where the traffic stream is folded back to the source. 000 = Normal operation 001 = Near-end PCS Loopback 010 = Near-end PMA Loopback 011 = Reserved 100 = Far-end PMA Loopback 101 = Reserved 110 = Far-end PCS Loopback

Table 2-53: TX System Reset⁽¹⁾
Bits	Default Value	Description
0	0	Reset all the TX logic. Writing 1 to this bit will reset both the TX channel datapath logic and the PLL selected for use by the TX. This bit does not self clear.
Notes: 1.The PHY IP core contains a single TX System Reset register which can be programmed to any index.

Table 2-54: RX System Reset⁽¹⁾
Bits	Default Value	Description
0	0	Reset all the RX logic. Writing 1 to this bit will reset both the RX channel datapath logic and the PLL selected for use by the RX. This bit does not self clear.
Notes: 1.The PHY IP core contains a single RX System Reset register which can be programmed to any index.

Table 2-55: cpll_cal_period⁽¹⁾
Bits	Default Value	Description
17:0	-	This register is set by default to the correct value for the line rate configuration specified in the IP AMD Vivado™ Integrated Design Environment (IDE). When changing line rate dynamically and using the CPLL, failure to set this register correctly might result in the JESD204_PHY failing to come out of reset. This register must be programed with the value calculated as follows: ((CPLL_VCO_FREQUENCY / 20.0) * (16000 / (4.0 * DRPCLK_FREQUENCY))) Refer to UG576 [Ref 10] and UG578 [Ref 11] for details on how to determine CPLL_VCO_FREQUENCY. DRPCLK_FREQUENCY is the values specified in the IP Vivado IDE.
Notes: 1.The PHY IP core contains a single cpll_cal_period register which can be programmed to any index.

Table 2-56: cpll_cal_tolerance⁽¹⁾
Bits	Default Value	Description
17:0	-	This register will be set by default to the correct value for the line rate configuration specified in the IP Vivado IDE. When changing line rate dynamically and using the CPLL, failure to set this register correctly might result in the JESD204_PHY failing to come out of reset. This register must be programed with the value calculated as follows: ((CPLL_VCO_FREQUENCY / 20.0) * (16000 / (400.0 * DRPCLK_FREQUENCY))) See UG576 [Ref 10] and UG578 [Ref 11] for details on how to determine CPLL_VCO_FREQUENCY. DRPCLK_FREQUENCY is the values specified in the IP GUI.
Notes: 1.The PHY IP core contains a single cpll_cal_tolerance register which can be programmed to any index.

Table 2-57: TXPD
Bits	Default Value	Description
1:0	0	Power up or down the TX of the GT transceiver. 00 = Power state for normal operation. 11 = Power saving state with lowest power.

Table 2-58: TXDIFFCTRL
Bits	Default Value	Description
N:0⁽¹⁾	4'b1100	Driver Swing Control.
Notes: 1.‘N’ is transceiver dependent - refer to the relevant transceiver user guide.

Table 2-59: TXINHIBIT
Bits	Default Value	Description
0	0	When High, this signal blocks transmission of TXDATA and forces MGTHTXP to 0 and MGTHTXN to 1.

Table 2-60: TXPOLARITY
Bits	Default Value	Description
0	0	The TXPOLARITY port is used to invert the polarity of outgoing data. 0 = Not inverted. TXP is +ve, and TXN is -ve. 1 = Inverted. TXP is -ve, and TXN is +ve.

Table 2-61: TXPRBSSEL
Bits	Default Value	Description
3:0	0	Transmitter PRBS generator test pattern control. See UG576 [Ref 10] and UG578 [Ref 11] for details.

Table 2-62: TXOUTCLKSEL
Bits	Default Value	Description
2:0	0	TX output clock multiplexer select. This selects the source of TXOUTCLK. See UG576 [Ref 10] and UG578 [Ref 11] for details.
Notes: 1.For TXPRBS operation, the TXOUTCLK must be used as the source of tx_core_clk to the JESD204_PHY and JESD204C IP cores. For details, see Configuring PRBS Test Modes. If an external clock source is used instead, then a clock multiplexor should be added to the design to switch between the external source clock and the TXOUTCLK. For detailed design instructions, generate the JESD204C example design and check the top level file jesd204c_exdes.v for commented RTL and constraints information.

Transceiver Control - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)