This chapter contains information about the test bench provided in the AMD Vivado™ Design Suite. The following figure shows the test bench block diagram.
Hierarchy is used extensively to create per-lane stimulus and checker blocks which allow easier signal viewing in the waveform window.
The test bench provides all clocks required by the design. If the TX and RX line rates and standard version are equal, the loopback path is automatically selected for simulation at IP build time.
Several event messaging functions exist at the top-level. These indicate when the lanes are out of reset and the bit rates used by the RX and TX channels. A timeout function is also included.
The data generation and testing functions exist in separate modules instantiated in the top-level test bench. This enables clear navigation to a lane data stream with the waveform viewer. The data stream starts when both the TX and RX paths are out of reset. K28.5 (/K/) symbols are transmitted to allow the transceivers to bit align.
In JESD204C configurations a byte incrementing data pattern is sent. The header value alternates between 1 and 2.
Note: The TX serial data and clock recovery Verilog module can be reused as a plugin serial line decoder for the GT output. The bit period is measured and data sampled and decoded accordingly. This can be a useful method for debugging designs created in IPI.
Similarly, the RX generator can be reused as a GT data injection module for a custom test bench.
IMPORTANT: To change any IP parameters, you must reconfigure the IP and regenerate the example design.