The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
01/30/2025 |
4.1 |
Removed support for JESD204B LogiCORE and 7 Series devices. |
|
04/08/2021 |
4.0 |
•Added clock domain information to Table: TX Parallel Data Interface Ports – JESD204C Configuration, Table: TX: Transceiver Serial Interface Ports, Table: RX Parallel Data Interface Ports – JESD204C Configuration, and Table: RX: Transceiver Serial Data Interface Ports. •Added TXPRBSSEL and TXOUTCLKSEL to Table: Register Address Map. •Added Table: TXPRBSSEL and Table: TXOUTCLKSEL. •Added Configuring PRBS Test Modes. |
|
06/03/2020 |
4.0 |
•Added support for GTH-based devices to JESD204C core for both 8B10B and 64B66B line coding. |
|
10/04/2017 |
4.0 |
•Added support for JESD204C IP LogiCORE. •Added new parameters Tx_JesdVersion and Rx_JesdVersion to support choosing between JESD204B and JESD204C interfaces. •Added 8B10B signaling ports to 64bit JESD204C interfaces. |
|
06/07/2017 |
3.4 |
•Added port GT_POWERGOOD for UltraScale and UltraScale+ devices. •Added new cpll_cal registers for UltraScale+. |
|
04/05/2017 |
3.3 |
For 64-bit interface only. The following ports were removed: •tx/rx_core_clk_out •tx/rx_userclk •tx/rx_userclk_out •and tx/rx_core_clk was added |
|
10/05/2016 |
3.2 |
•Added new configuration parameters for static and dynamic line rate and insertion loss at Nyquist •Added ports rxencommaalign and pcsrsvdin |
|
06/08/2016 |
3.1 |
•Updated System Reset section. •Updated and clarified RXLPMEN and TXDIFFCTRL registers. |
|
04/06/2016 |
3.1 |
•Added support for 64 bit interface with 64b/66b encoding •Added support for UltraScale+ |
|
11/18/2015 |
3.0 |
Added support for UltraScale+ families. |
|
09/30/2015 |
3.0 |
•Resource Utilization removed (now online). •Updated Figures 1-1 and 1-2 to add tx/rx_sys_reset signals. •Added support for GTY Transceivers. •Removed registers Common DRP select (0x100) and PLL select (0x300 •Removed registers Transceiver DRP select (0x200), Transceiver Select Bank 1 (0x400), Transceiver Select Bank 2 (0x500), Transceiver Select Bank 3 (0x600) •Added mmcm_lock ports for GTP transceivers |
|
04/01/2015 |
2.0 |
•Updated Applications section. •Added GT Port important note in Transceiver Control and Status Ports section. •Updated Table 2-4: Common Clock and Reset Ports. •Added qpll0_reset_out and qpll1_reset_out to Table 2-5: Clocks and Resets for Shared Logic in Example Design. •Added Register Space and Line Rate Switching section. •Added JESD204 PHY Configuration Options section. •Updated Clocking section. •Updated Fig. 4-1: Configuration Tab. •Added Optional Settings in Configuration Tab section. •Updated User Parameters. •Added constraint file in Required Constraints section. •Added UNISIM important note in Simulation section. •Added AXI Interface section in Test Bench chapter. |
|
10/01/2014 |
1.0 |
Initial Xilinx release. |