Receiver Interface Ports - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)
Document ID
PG198
Release Date
2025-01-30
Version
4.1 English

The receiver interface ports available on the JESD204 PHY core are shown in Table: RX Parallel Data Interface Ports – JESD204C Configuration.

 

Table 2-7:      RX Parallel Data Interface Ports – JESD204C Configuration

Signal Name

I/O

Clock Domain

Description

gtN_rxdata[63:0]

O

rx_core_clock

Data to RX core. N = 0 … [Lanes – 1]

gtN_rxheader[1:0]

O

rx_core_clock

Header flag to RX core.

gtN_rxblock_sync

O

rx_core_clock

Block alignment flag to RX core. N = 0 … [Lanes – 1]

gtN_rxmisalign

O

rx_core_clock

Block misaligned flag to RX core, block had invalid header.
N = 0 … [Lanes – 1]

gtN_rxcharisk[3:0]

O

rx_core_clock

Char is K to RX core. N = 0 … [Lanes – 1]

gtN_rxdisperr[3:0]

O

rx_core_clock

Disparity error to RX core. N = 0 … [Lanes – 1]

gtN_rxnotintable[3:0]

O

rx_core_clock

Not In Table to RX core. N = 0 …[Lanes – 1]
Table 2-8:      RX: Transceiver Serial Data Interface Ports

Signal Name

I/O

Clock Domain

Description

rxp_in[N:0]

I

rx_core_clock

Positive differential serial data input N = (Lanes – 1)

rxn_in[N:0]

I

rx_core_clock

Negative differential serial data input N = (Lanes – 1)