QPLL0/1 - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)

Document ID
PG198
Release Date
2025-01-30
Version
4.1 English

The QPLL VCOs have different operating bands, see the device specific data sheet for more information.

The frequency out of the PLL is given by:

pg198-product-spec00015.jpg 

Where N = QPLL(0/1)_FBDIV and M = QPLL(0/1)_REFCLK_DIV.

Note:   For GTH, FractionalPart=1 and QPLL_CLKOUTRATE=2

To calculate the line rate use:

pg198-product-spec00017.jpg

 

Where D = (R/T)XOUT_DIV.

Table 2-73:      Valid Divider Settings

Factor

Attribute

Valid Settings

M

QPLL0_REFCLK_DIV

QPLL1_REFCLK_DIV

1, 2, 3, 4

N

QPLL0_FBDIV

QPLL1_FBDIV

16, 20, 32, 40, 64, 66, 80, 100

D

RXOUT_DIV

TXOUT_DIV

1, 2, 4, 8, 16

The following table shows addresses of interest as well as the bits and encoding that must be used to select the correct divider values when interpreting the register content.

Table 2-74:      DRP Address Map

DRP Addr (Hex)

DRP Bits

R/W

Attribute Name

Bits

Encoding

DRP Encoding

0008

15:0

R/W

QPLL0_CFG0

15:0

0 to 65535

0 to 65535

0009

15:0

R/W

COMMON_CFG0

15:0

0 to 65535

0 to 65535

0010

15:0

R/W

QPLL0_CFG1

15:0

0 to 65535

0 to 65535

0011

15:0

R/W

QPLL0_CFG2

15:0

0 to 65535

0 to 65535

0014

7:0

R/W

QPLL0_FBDIV

7:0

16

14

20

18

32

30

40

38

64

62

66

64

80

78

100

98

0018

11:7

R/W

QPLL0_REFCLK_DIV

7:0

1

16

2

0

3

1

4

2

0088

15:0

R/W

QPLL1_CFG0

15:0

0 to 65535

0 to 65535

0089

15:0

R/W

COMMON_CFG1

15:0

0 to 65535

0 to 65535

0090

15:0

R/W

QPLL1_CFG1

15:0

0 to 65535

0 to 65535

0091

15:0

R/W

QPLL1_CFG2

15:0

0 to 65535

0 to 65535

0094

7:0

R/W

QPLL1_FBDIV

7:0

16

14

20

18

32

30

40

38

64

62

66

64

80

78

100

98

0098

11:7

R/W

QPLL1_REFCLK_DIV

7:0

1

16

2

0

3

1

4

2