Port Descriptions - 4.1 English

This section contains details about the JESD204 PHY ports.

The following tables detail the ports available when the core is configured for shared logic in the core or in the example design.

The following two tables list the Common Clock and Reset Ports for JESD204C Configurations (Shared Logic in Core).

Table 2-1: Common Clock Ports - JESD204C Configurations (Shared Logic in Core)
Signal Name⁽¹⁾	I/O	Description
txoutclk	O	Output clock from transceiver. This clock is sourced from the TX master channel, which is selected from the GUI in the JESD PHY core.
rxoutclk	O	Output clock from transceiver. This clock is sourced from the RX master channel, which is selected from the GUI in the JESD PHY core.
gt_powergood	O	Core output set to indicate the transceiver power is good. This output is set after device configuration. This output is only available on UltraScale and UltraScale+ devices.
tx_core_clk	I	Core clock used to drive txusrclk and txuserclk2 of transceiver. Frequency = serial line rate/66
rx_core_clk	I	Core clock used to drive rxusrclk and rxuserclk2 of transceiver. Frequency = serial line rate/66
drp_clk	I	Dynamic Reconfiguration Port (DRP) clock.
cpll_refclk	I	Reference clock for the Transceiver Channel PLL.
qpll0/1_refclk	I	Reference clock for the Quad Common PLL(s).
commonM_qpll0_clk_out	O	Clock output from the QPLL (Quad M). Only present when QPLL0 is enabled.
commonM_qpll0_refclk_out	O	Reference clock output from the QPLL (Quad M). Only present when QPLL0 is enabled.
commonM_qpll0_lock_out	O	Lock output from the QPLL0 (Quad M). Only present when QPLL0 is enabled.
commonM_qpll1_clk_out	O	Clock output from the QPLL (Quad M). Only present when QPLL1 is enabled.
commonM_qpll1_refclk_out	O	Reference clock output from the QPLL (Quad M). Only present when QPLL1 is enabled.
commonM_qpll1_lock_out	O	Lock output from the QPLL1 (Quad M). Only present when QPLL1 enabled.
Notes: 1.M = Number of QUADs – 1

Table 2-2: Common Reset Ports - JESD204C Configurations (Shared Logic in Core)
Signal Name⁽¹⁾	I/O	Description
tx_reset_gt	I	TX channel datapath asynchronous logic reset.
rx_reset_gt	I	RX channel datapath asynchronous logic reset.
tx_sys_reset	I	TX channel datapath and PLL asynchronous logic reset.
rx_sys_reset	I	RX channel datapath and PLL asynchronous logic reset.
Notes: 1.M = Number of QUADs – 1

The following two tables list the Common Clock and Reset Ports for JESD204C Configurations (Shared Logic in Example Design).

Table 2-3: Common Clock Ports for JESD204C Configurations (Shared Logic in Example Design)
Signal Name	I/O	Description
drp_clk	I	Dynamic Reconfiguration Port (DRP) clock.
cpll_refclk	I	Reference clock for the Transceiver Channel PLL.
qpll0/1_refclk	I	Reference clock for the Quad Common PLL(s) in UltraScale and UltraScale+ devices.
tx_core_clk	I	Core clock used to drive txusrclk2 of transceiver. Frequency = serial line rate/66.
rx_core_clk	I	Core clock used to drive rxusrclk2 of transceiver. Frequency = serial line rate/66.
commonM_qpll0_clk_in	I	Clock input for the QPLL (Quad M). Only present when QPLL0 is selected.
commonM_qpll0_refclk_in	I	Reference clock input for the QPLL (Quad M). Only present when QPLL0 is selected.
commonM_qpll1_clk_in	I	Clock input for the QPLL (Quad M). Only present when QPLL1 is selected.
commonM_qpll1_refclk_in	I	Reference clock input for the QPLL (Quad M). Only present when QPLL1 is selected.

Table 2-4: Common Reset Ports for JESD204C Configurations (Shared Logic in Example Design)
Signal Name	I/O	Description
tx_reset_gt	I	TX channel datapath asynchronous logic reset.
rx_reset_gt	I	RX channel datapath asynchronous logic reset.
tx_sys_reset	I	TX channel datapath and PLL asynchronous logic reset.
tx_sys_reset	I	TX channel datapath and PLL asynchronous logic reset.
qpll0_reset_out	O	Reset output from transceiver logic to reset QPLL0 Common Block when QPLL0 is selected or the AXI4-Lite Management Interface is enabled and at least one channel is using either QPLL0 or QLL1.
qpll1_reset_out	O	Reset output from transceiver logic to reset QPLL1 Common Block when QPLL1 is selected or the AXI4-Lite Management Interface is enabled and at least one channel is using either QPLL0 or QLL1.

Port Descriptions - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)