Overview - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)
Document ID
PG198
Release Date
2025-01-30
Version
4.1 English

The LogiCORE™ IP JESD204 PHY core implements a JESD204C Physical interface supporting line rates between 1.0 and 32 Gb/s on 1 to 8 lanes for AMD UltraScale™ and AMD UltraScale+™ devices.

See the relevant user guide for specific line rates supported by each device (Table: Transceiver User Guides):

Table 1-1:      Transceiver User Guides

UltraScale

UltraScale+

GTHE3 [Ref 10]

GTHE4 [Ref 10](1)

GTYE3 [Ref 11]

GTYE4 [Ref 11](1)

1.For certain UltraScale+ device speed grades, when using 8B10B line coding, the line rate might also be limited by the maximum frequency specified for TXUSRCLK/RXUSERCLK (core clock) with 40-bit Interconnect Logic Data width.
The maximum line rate in these devices is TX/RXUSERCLK * 40. Refer to the relevant device data sheet.

The JESD204 PHY core can be configured with independent transmit and receive line rates and JESD204 standard version support.

The following figure shows the JESD204 PHY core with shared logic in the example design.

Figure 1-1:      JESD204 PHY Block Diagram – Shared Logic in Example Design

X-Ref Target - Figure 1-1

phyCoreNonShared.jpg

The following figure shows a block diagram of the JESD204 PHY core with shared logic in the core.

Figure 1-2:      JESD204 PHY Block Diagram – Shared Logic in Core

X-Ref Target - Figure 1-2

phyCoreShared.jpg

When used with the JESD204C core, the JESD204 PHY core is a fully-verified solution design delivered by using the AMD Vivado™ Design Suite. In addition, an example design is provided in Verilog. For more information, see the JESD204C LogiCORE IP Product Guide (PG242) [Ref 15].