The recommended sequence for line rate switching is as follows:
Note: The JESD204 PHY core must be generated with the Dynamic Line Rate option selected in the Line rate Switching section in the Vivado Integrated Design Environment (IDE).
•Ensure all valid data has been sent/received
•Power down the PLL (optional)
•Modify the PLL dividers through the appropriate DRP interface
•Select the correct refclk source for each transceiver in RX and TX
•Note if only using one direction the other can be powered down
•Adjust any other control signals
°If using an UltraScale+ device, ensure the cpll_cal_period and cpll_cal_tolerance registers are programmed. Failure to do so might result in the JESD204_PHY failing to come out of reset.
•Power up the PLLs (can be optional)
•Reset the PLL