The JESD204C configuration example design uses a sequencer module which is responsible for enabling data generation and data checking on the RX side.
A rolling 8-bit counter is used to generate data, which is replicated for each byte in the interface.
Rollover from 255 alternates from 0 to 1 to allow the block alignment functions to be able to detect the 01 or 10 header bits correctly. Header values of 00 and 11 are considered invalid.
The following two figures show the clock structure for different and identical PLL types respectively.
Note: If different PLLs are selected for the RX and TX paths, the port names for refclk are named as RX and TX. If they are the same, the port is named common.
|
X-Ref Target - Figure 5-2 |
|
X-Ref Target - Figure 5-3 |