The JESD204 PHY can be generated in eight main logical configurations.
Note: The JESD204C TX/RX interfaces can only be connected with the JESD204C IP.
|
AXI Enabled |
Shared Logic |
Transceiver Debug |
Description |
|---|---|---|---|
|
0 |
0 |
0 |
No AXI interface logic present, no COMMON PLL (QPLL) logic. |
|
0 |
0 |
1 |
No AXI interface logic present, no COMMON PLL (QPLL) logic, the current JESD204_PHY transceiver debug ports list is present. |
|
0 |
1 |
0 |
No AXI interface logic present, COMMON PLL (QPLL) logic included in core. |
|
0 |
1 |
1 |
No AXI interface logic present, COMMON PLL (QPLL) logic included in core, current JESD204_PHY transceiver debug ports list present. |
|
1 |
0 |
0 |
AXI interface logic present, no COMMON PLL (QPLL) logic or COMMON PLL AXI control registers. Transceiver debug ports are present, minus the ports mapped to AXI control interface registers. |
|
1 |
0 |
1 |
AXI interface logic present, no COMMON PLL (QPLL) logic or COMMON PLL |
|
1 |
1 |
0 |
AXI interface logic present, COMMON PLL (QPLL) logic included in core. |
|
1 |
1 |
1 |
AXI interface logic present, COMMON PLL (QPLL) logic in core, transceiver debug ports are present, minus the ports mapped to AXI control interface registers. |
The common PLL DRP interface is not presented at the JESD204 PHY core output ports under any circumstance and can only be accessed with the AXI interface enabled and a QPLL selected as a refclk source.
In AMD UltraScale™ and AMD UltraScale+™ devices, when the AXI interface logic is enabled and QPLL0/1 is selected as one of the PLLs, both PLL refclk ports appear. This is different to non-AXI mode where only the refclk of the selected PLL appears. This is to maximize flexibility when using the AXI interface for line rate switching.