•Ensure that all the timing constraints for the core were met during implementation.
•Ensure that all clock sources are clean and in particular that the JESD204 PHY’s clocks meet the GTH/GTY transceiver requirements from the appropriate FPGA Data Sheet.
•Ensure that all GTH/GTY transceiver PLLs have obtained lock by monitoring the QPLLLOCK_OUT and/or CPLLLOCK_OUT port using the debug feature.
•Ensure that the core is correctly wired up.