•Designed to JEDEC® JESD204B [Ref 1] and JEDEC JESD204C [Ref 14]
•Supports 1 to 8 lanes when using the JESD204C IP core
•Supports Subclass 0, 1, and 2
•Physical Layer functions provided
•Supports transceiver sharing between TX and RX cores
•Optional AXI interface with AXI to DRP bridges for QPLL and Transceiver access
•AXI interface enables line rate switching
•AXI register allows control of selected transceiver signals
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LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family(1) |
AMD UltraScale+™, AMD UltraScale™ |
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Supported User Interfaces |
N/A |
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Resources |
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Provided with Core |
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Design Files |
RTL |
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Example Design |
Verilog |
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Test Bench |
Verilog |
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Constraints File |
XDC |
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Simulation Model |
Verilog |
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Supported |
N/A |
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Tested Design Flows(2) |
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Design Entry |
AMD Vivado™ Design Suite |
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Simulation |
For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing. |
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 61911 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1.For a complete list of supported devices, see the Vivado IP catalog. 2.For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing. |
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