This chapter contains information about the example design provided in the AMD Vivado™ Design Suite.
Although the JESD204 PHY core is not intended to be used as a standalone solution, an example design is provided for the IP core. The example design is a lightweight harness that can operate in an external TX to RX loopback mode, or in an independent RX/TX channel mode.
See the example design provided with the JESD204C IP for a more detailed use case example [Ref 15].
Note: 8b/10b and 64b/66b are incompatible line coding schemes. So even when a matching line rate is chosen, and the TX and RX direction are of different data widths, the demo_tb loopback mode will not be used.
To open the example design, right-click the IP and select Open IP Example Design as shown in the following figure.