The DRP mailbox interface gives complete access to the common and transceiver DRP address maps as given in the following:
•UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 10]
•UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 11]
AMD recommends to reference the appropriate user guide, along with the data sheet for minimum/maximum refclk frequencies, line rates, etc. for the correct speed/package combination as well as consideration of system supply voltage.
The following sections highlight the registers of interest in the DRP register space when line rate switching. In general, the DRP registers are tightly packed and read modify write sequences should be used to modify the required bits.