The JESD204 PHY core operates using a 64-bit (8-byte) datapath plus a 2 bit header. The device clock for the core logic therefore runs at 1/ 66th of the serial line rate. For the JESD204C and JESD204 PHY cores, this is referred to as the core clock. This clock must be supplied externally to the core, and must be derived from the same clock source as the REFCLK supplied to the transceiver.