•Configuration Preset
°Physical Resources
-Lanes per Link - The core supports 1 to 8 lanes for JESD204C. The number of transmit lanes always matches the number of receive lanes. For asymmetric interfaces, multiple cores can be generated and multiple JESD204 PHY cores can be connected to a single JESD204C core.
-Transceiver Type - For Devices with Multiple transceiver types, this option allows the selection of transceiver type for which to generate the core.
-Starting Transceiver Location - Select starting location of lane 0. This allows Vivado to generate the correct location constraints for the transceiver during IP generation.
°Line Rate Switching
-Line Rate Capabilities - Select “Static” or “Dynamic” Line rate. This controls how the core is generated. Selecting “Static” generates a design that is exactly as specified in the GUI. Selecting “Dynamic” generates a core with the defaults set to exactly as specified in the GUI, but it will also include any additional logic required to switch via software control to any line rate between the following minimum and maximum values:
Minimum Line Rate - Set the minimum line rate value required for dynamic line rate switching.
Maximum Line Rate - Set the Maximum line rate required for line dynamic line rate switching.
•Transceiver Parameters, Transmitter, and Receiver
°JESD204 Version – The version of the JESD204 standard intended to interface with. Hard coded to JESD204C. The JESD204B core is no longer supported.
°Line Coding – Select either 8B10B or 64B66B line coding options with the JESD204C core.
°Line Rate – The serial line rate in Gb/s can be selected for transmit and receive independently. The minimum rate is 1 Gb/s and the maximum depends on the chosen device and speed grade. If the core is generated with dynamic line rate switching capability, these values are the default configuration at power up.
°Reference Clock – The reference clock must be selected from the drop-down list, which presents a list of valid reference clock frequencies for the selected line rate. Independent reference clocks can only be selected if different PLLs are selected for transmit and receive. If the core is generated with dynamic line rate switching capability these values are the default configuration at power up.
°PLL Type – Select the QPLL or CPLL for transmit and receive. See the appropriate device transceiver user guide for more details and limitations. If the core is generated with dynamic line rate switching capability these values are the default configuration at power up. If dynamic switching between PLL types (QPLL / CPLL) is required, the core must be generated with TX/RX set to use one of each type.
°Master channel – Select the transceiver channel to source TX/RXOUTCLK from. This channel should not be powered down if TX/RXOUTCLK is used, as this will switch off the CLK.
°DRP Clock Frequency – The frequency of the DRP clock being applied to the core. This value must match the frequency actually supplied to the pin so that reset delays can be adjusted by the reset and calibration state machines. Failure to supply the correct frequency may result in the JESD204_PHY failing to complete reset.
•Advanced (Receiver only)
°Channel Attenuation – Select RX equalization mode, Auto, Low loss or High Loss. Refer to the appropriate transceiver user guide for more information.
This parameter affects the value set on the RXLPMEN port into the transceiver.
Low loss = LPM
High Loss = DFE
Auto = LPM or DFE selected automatically based on Insertion Loss at Nyquist and RX Line rate.
°Insertion loss at Nyquist - Enter the insertion loss at Nyquist of the channel.
Note: It is not recommended to change this value from the default.
•Optional Settings
°AXI4-Lite Management Interface – Select to include the AXI4-Lite configuration interface. This allows AXI-based access to the Transceiver and Common DRPs.
°AXI4-Lite Clock Frequency – The AXI4-Lite clock can be connected to the main processor clock. When applicable, the clock domain boundary crossings are handled inside the IP to simplify implementation. Also, when a clock boundary is involved the AXI access is stretched, resulting in an extended access time.
•Transceiver Debug – Select to include additional transceiver control and status ports for debugging purposes. See Transceiver Debug Interface for more information.