Common/Transceiver DRP Control - 4.1 English

The DRP interface provides an “indirect mailbox” mechanism for read/write to multiple DRPs. Bits[31:30] of the DRP Address are used to auto-initiate a read or write of the DRP interface. A Status register is provided to allow you to check the access has completed without error. There are two mailboxes, one at 0x1XX for the COMMON DRPs and one at 0x2XX for the transceiver DRPs.

For accesses to the Common DRP mailboxes, ensure that register cmm_interface_sel (0x020) is programmed with index of the Common DRP that is required. The range is 0 to N-1, where N is the value returned in the “Number of Common interfaces” register (0x008).

For accesses to the Transceiver DRP mailboxes, ensure that register gt_interface_sel (0x024) is programmed with the index of the Transceiver DRP that is required. The range is 0 to M-1, where M is the value returned in the “Number of Transceiver interfaces” register (0x00C).

Table 2-38: Common/Transceiver DRP Address
Bits	Default Value	Description
31	–	Set to 1 to perform a write to the DRP.
30	–	Set to 1 to perform a read from the DRP.
29:0	–	DRP register address Only the LS Bits of the address will be used depending on the address width of the transceiver used. The unused MS Bits should be ignored. See one of the following for a complete DRP address map: •UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 10] •UltraScale Architecture GTY Transceivers (UG578) [Ref 11]
Notes: 1.The lower Bits[29:0] can be read/written without triggering a DRP access allowing the firmware to test the address value if required. If both upper bits are set the access is ignored because the DRP cannot be read/written at the same time. This results in 0x0 being read in these upper two bits.

Table 2-39: Common/Transceiver DRP Write Data
Bits	Default Value	Description
31:16	–	Reserved, the DRP registers are all 16 bits
15:0	–	Data to be written to the selected DRP register

Table 2-40: Common/Transceiver DRP Read Data
Bits	Default Value	Description
31:16	–	Reserved, the DRP registers are all 16 bits
15:0	–	Data read back from the selected DRP register

Table 2-41: Common/Transceiver DRP Reset
Bits	Default Value	Description
31:1	–	Reserved
0	0	Write a 1 to reset the DRP interface. Self-clearing.

Table 2-42: Common/Transceiver DRP Access Status
Bits	Default Value	Description
31:3	–	Reserved
2	–	Access Type 0 = read 1 = write This register is only set when “DRP Access in Progress” bit is set to allow a read of all zeros check of the register for completion. Sticky on Timeout Error, updated on new DRP access.
1	–	Reserved
0	–	DRP Access in Progress Set on a write of 1 to either of the top two bits of DRP Address register and auto cleared when DRP data is valid.

Table 2-43: Common/Transceiver DRP Access Complete
Bits	Default Value	Description
31:1	–	Reserved
0	–	When asset to 1, the AXI4-Lite does not complete the final write to the DRP Address register until the DRP access has completed. When set, there is no need to poll the DRP Access in Progress bit of the DRP Access Status register.

Common/Transceiver DRP Control - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)