Common QPLL Control - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)

Document ID
PG198
Release Date
2025-01-30
Version
4.1 English

For accesses to the Common QPLL Control registers ensure that register cmm_interface_sel (0x020) is programmed with index of the Common QPLL that is required. The range is 0 to N-1, where N is the value returned in the “Number of Common interfaces” register (0x008).

Table 2-44:      QPLL0 Power Down

Bits

Default Value

Description

0

0

1 = Power Down QPLL0

Register Address Map

Table 2-45:      QPLL1 Power Down

Bits

Default Value

Description

0

0

1 = Power Down QPLL1

Register Address Map