This section describes the options available for clocking the JESD204 PHY core and the transceiver(s). The following clocks are used in the JESD204 PHY core.
•DRP Clock – The transceiver requires an auxiliary clock for internal use and also for the reset state machines within the JESD204 PHY core. See the appropriate device family data sheet for the min and max DRP clock frequencies permitted.
•Reference Clock – The GTH/GTY serial transceivers require a stable, low-jitter reference clock that has a device and speed grade dependent range. In some circumstances, the same source clock can supply both the reference clock and core clock. Multiple reference clocks might be required if multiple PLLs are selected in the GUI.
•AXI4-Lite Configuration Interface Clock – Required if the AXI is enabled. This is asynchronous to any other clock and can be driven by the processor subsystem.