CPLL - 4.1 English - PG198

JESD204 PHY v4.1 Product Guide (PG198)

Document ID
PG198
Release Date
2025-01-30
Version
4.1 English

The CPLL operating limits vary for each transceiver type. See the device specific data sheet for more information.

The frequency out of the PLL is given by:

pg198-product-spec00019.jpg

 

Where N = QPLL(0/1)_FBDIV and M = QPLL(0/1)_REFCLK_DIV.

To calculate the line rate use:

pg198-product-spec00021.jpg

 

Where D = (R/T)XOUT_DIV.

Table 2-75:      Valid Divider Settings

Factor

Attribute

Valid Settings

M

CPLL_REFCLK_DIV

1, 2

N2

CPLL_FBDIV

1, 2, 3, 4, 5

N1

CPLL_FBDIV_45

4, 5

D

RXOUT_DIV
TXOUT_DIV

1, 2, 4, 8

Table: DRP Address Map shows the addresses of interest as well as the bits and encoding that must be used to select the correct divider values when interpreting the register content.

Table 2-76:      DRP Address Map

DRP Addr
(Hex)

DRP Bits

R/W

Attribute
Name

Bits

Encoding

DRP
Encoding

Notes

0028

15:8

R/W

CPLL_FBDIV

7:0

1

16

N2

2

0

3

1

4

2

5

3

0028

7

R/W

CPLL_FB_DIV_45

0

4

0

N1

5

1

002A

15:11

R/W

CPLL_REFCLK_DIV

4:0

1

16

M

2

0

002B

15:0

R/W

CPLL_INIT_CFG0

15:0

0 to 65535

0 to 65535