The CPLL operating limits vary for each transceiver type. See the device specific data sheet for more information.
The frequency out of the PLL is given by:
Where N = QPLL(0/1)_FBDIV and M = QPLL(0/1)_REFCLK_DIV.
To calculate the line rate use:
Where D = (R/T)XOUT_DIV.
|
Factor |
Attribute |
Valid Settings |
|---|---|---|
|
M |
CPLL_REFCLK_DIV |
1, 2 |
|
N2 |
CPLL_FBDIV |
1, 2, 3, 4, 5 |
|
N1 |
CPLL_FBDIV_45 |
4, 5 |
|
D |
RXOUT_DIV |
1, 2, 4, 8 |
Table: DRP Address Map shows the addresses of interest as well as the bits and encoding that must be used to select the correct divider values when interpreting the register content.