AXI4-Lite Register Space - 4.1 English - PG198

0x000

Version

R

0x004

IP Configuration

R

0x008

Number of Common Interfaces

R

0x00C

Number of Transceiver Interfaces

R

0x014

Timeout Enable

R/W

0x018

Reserved

–

0x01C

Timeout Value

R/W

0x020

Common Interface Selector

R/W

0x024

GT Interface Selector

R/W

0x028 to 0x07F

Reserved

–

0x030

Transceiver Master Channel for RX

R

0x034

Transceiver Master Channel for TX

R

0x038

RX Interface Line Coding

R

0x03C

TX Interface Line Coding

R

0x080

PLL Status

R

0x084 to 0x0FF

Reserved

–

0x90

RXLINERATE

R

0x98

RXREFCLK

R

0x9C

RXXMULT

R

0xA0

RXPLL

R

0xB0

TXLINERATE

R

0xB8

TXREFCLK

R

0xBC

TXXMULT

R

0xC0

TXPLL

R

0xD0

SW_CAPABLE

R

0xD4

INS_LOSS

R

0xD8

EQUALISATION

R

0xE0

MIN_RATE

R

0xE4

MAX_RATE

R

0xE8

DRPCLK

R

Common/Transceiver DRP Control

0x104/0x204

Common/Transceiver DRP Address

R/W

0x108/0x208

Common/Transceiver DRP Write Data

R/W

0x10C/0x20C

Common/Transceiver DRP Read Data

R

0x110/0x210

Common/Transceiver DRP Reset

R/W

0x114/0x214

Common/Transceiver DRP Access Status

R

0x118/0x218

Reserved

–

0x11C/0x21C

Common/Transceiver DRP Access Complete

R

0x120 to 0x1FF/0x220 to 0x2FF

Reserved

–

Common QPLL Control

0x304

QPLL0 Power Down

R/W

0x308

QPLL1 Power Down

R/W

0x30C to 0x3FF

Reserved

–

Transceiver Control – Bank 1

0x404

RXPD (RX Power Down)

R/W

0x408

CPLLPD (CPLL Power Down)

R/W

0x40C

Transmit PLL Clock Select(1)

R/W

0x410

Receive PLL Clock Select(1)

R/W

0x414

TX Postcursor

R/W

0x418

TX Precursor

R/W

0x41C

Loopback

R/W

0x420

TX System Reset(1)

R/W

0x424

RX System Reset(1)

R/W

0x430

cpll_cal_period(1)

R/W

0x434

cpll_cal_tolerance(1)

R/W

0x438 to 0x4FF

Reserved

–

Transceiver Control – Bank 2

0x504

TXPD

R/W

0x508

TXDIFFCTRL

R/W

0x50C

TXINHIBIT

R/W

0x510

TXPOLARITY

R/W

0x520

TXPRBSSEL

R/W

0X524

TXOUTCLKSEL

R/W

0x528 to 0x5FF

Reserved

–

Transceiver Control – Bank 3

0x604

RXPOLARITY

R/W

0x608

RXLPMEN

R/W

0x60C

RXDFELPMRESET

R/W

0x610

RX Invalid SYNC Header Max (RX 64 bit only)

R/W

0x614 to 0x6FF

Reserved

–

31:24

–

Version: Major

23:16

–

Version: Minor

15:8

–

Version: Revision

7:0

–

Reserved (read 0x00)

31:24

–

FPGA Type:
1 = UltraScale
2 = UltraScale+
All other values are reserved.

23:16

–

Speed Grade:

10 = 1
11 = 1L
12 = 1H
13 = 1HV
14 = 1LV
20 = 2
21 = 2L
22 = 2LV
30 = 3
All other values are reserved.

15:8

–

Package:

1 = rf
2 = fl
3 = ff
4 = fb
5 = hc
6 = fh
7 = cs
8 = cp
9 = ft
10 = fg
11 = sb
12 = rb
13 = rs
14 = cl
15 = sf
16 = ba
17 = fa
All other values are reserved.

7:0

–

Transceiver Type:

5 = GTHE3
6 = GTYE3
7 = GTHE4
8 = GTYE4
All other values are reserved.

31:0

–

Reading this register returns the number of GT_COMMON blocks in the core. Normally one common block is included per four transceivers.

See the following documents for details:

°UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 10]

°UltraScale Architecture GTY Transceiver User Guide (UG578) [Ref 11]

The number returned here can be used by software to loop round the correct number of times to configure all the QPLLs in the core using the Common DRP control mailbox and the Common PLL control registers.

The valid range for the “Common interface select” register cmm_interface_sel (0x020), used to choose which Common PLL is being accessed, is 0 to N-1 where N is the value contained in this register.

31:0

–

Reading this register returns the number of GT_CHANNEL blocks (same as the number of lanes). The number returned here can be used by software to loop round the correct number of times to configure all the transceivers in the core using the Transceiver DRP control mailbox and the Transceiver control register banks.

The valid range for the “Transceiver interface select” register gt_interface_sel (0x024), used to choose which transceiver is being accessed, is 0 to N-1 where N is the value contained in this register.

31:1

–

Reserved

0

1

Enable the AXI4-Lite timeout. This ensures that transactions to the transceiver registers do not lock the AXI4-Lite bus which can happen if the transceiver is in reset or not being clocked when an access is attempted for example.

If a timeout occurs during an AXI transaction, it is indicated on the bresp bus as a SLVERR response, allowing the firmware to act accordingly.

31:12

–

Reserved

11:0

128

Set the number of AXI clock cycles to wait before terminating the AXI4-Lite access without completing.

If using timeout, the value must be modified according to the relationship between the AXI and DRP clock. The IP handles the DRP access by stretching the AXI interface response until it is completed. If the DRP clock is much slower than the AXI clock, this results in an unintentional timeout of the value is not increased. The timeout counts up so this value should be programmed with 4096-timeout.

The complete timeout length is this value + 2 cycles. Valid timeout value are 0 to 4094. Care must be taken to not set to small a value. Base setting this value on the slowest clock of the set, rx_core_clk, tx_core_clk, and drpclk.

31:2

–

Reserved

1:0

–

Set the number corresponding to the Common DRP control mailbox or the Common PLL control registers to be accessed. The range is 0 to N-1, where N is the value returned from the Number of Common Interfaces register (0x008).

31:4

–

Reserved

3:0

–

Set the number corresponding to the Transceiver DRP control mailbox or the Transceiver control register bank to be accessed. The range is 0 to N-1, where N is the value returned from the Number of Transceiver Interfaces register (0x00C).

31:4

–

Reserved

3:0

–

Returns master transceiver channel for RX.

31:4

–

Reserved

3:0

–

Returns master transceiver channel for TX.

31:1

–

Reserved

0

–

Returns operating mode of RX

1 = 64b66b bit mode
0 = 8b10b bit mode

31:1

–

Reserved

0

–

Returns operating mode of TX

1 = 64b66b bit mode
0 = 8b10b bit mode

31:5

–

Reserved

4

–

Returns 1 when a transmit reset is in progress.

3

–

Returns 1 when a receive reset is in progress.

2

–

Returns 0 when all the CPLLs are locked.

1

–

Returns 0 when all the QPLL0s are locked.

0

–

Returns 0 when all the QPLL1s are locked.

31:0

–

The default value of RX line rate that the core was generated to use.

Value in kHz.

31:0

–

The default value of RX refclk frequency that the core was generated to use.

Value in kHz.

31:0

–

The default value of RX xMult, the ratio between RX linerate and RX refclk, that the core was generated to use.

Value = linerate/refclk * 1000.

1:0

–

The default PLL for the RX path that the core was generated to use.

0 = CPLL
1 = QPLL0
2 = QPLL2

31:0

–

The default value of TX line rate that the core was generated to use.

Value in kHz.

31:0

–

The default value of TX refclk frequency that the core was generated to use.

Value in kHz.

31:0

–

The default TX xMult, the ratio between TX linerate and TX refclk, that the core was generated to use.

Value = linerate/refclk * 1000.

1:0

–

The default PLL for the TX path that the core was generated to use.

0 = CPLL
1 = QPLL0
2 = QPLL1

1:0

–

Line rate switching capability of the generated core

0 = Generated core not capable of line rate switching
1 = Generated core capable of line rate switching

31:0

–

The default RX Insertion loss that the core was generated to support.

Value = setting in dB from GUI * 1000

1:0

–

The default Equalization mode that the core was generated to use

0: Auto (Equalization mode set based on insertion loss)
1 = Low_Loss (Equalization mode LPM)
2 = High_Loss (Equalisation mode DFE)

31:0

–

The minimum line rate that the core was generated to use.

Value in kHz

31:0

–

The minimum line rate that the core was generated to use.

Value in kHz

31:0

-

The value of DRP clock frequency the core was generated to use. Value in kHz.