If the IP is generated with the AXI interface, this is presented in the test bench along with tasks to write/read over the interface. Basic examples are given at the start of the test, however the tasks might be used to test out custom sequences.
For AMD UltraScale™ and AMD UltraScale+™ GTH-based devices, see the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 10], Appendix B for a detailed DRP register map.
For UltraScale and UltraScale+ GTY-based devices, see the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 11].