SGDMA Descriptor Control Register (0x18) - SGDMA Descriptor Control Register (0x18) - v4.2 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document_ID
PG195
Release_Date
2026-07-22
Version
v4.2 English
Table 1. SGDMA Descriptor Control Register (0x18)
Bit Index Default Access Type Description
W1C Bit descriptions are the same as in SGDMA Descriptor Control Register (0x10).