SG Descriptor Mode Enable Register (0x24) - SG Descriptor Mode Enable Register (0x24) - v4.2 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document_ID
PG195
Release_Date
2026-07-22
Version
v4.2 English
Table 1. SG Descriptor Mode Enable Register (0x24)
Bit Index Default Access Type Description
W1S Bit descriptions are the same as in SGDMA Descriptor Credit Mode Enable (0x20).