New Ports - New Ports - 4.2 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document ID
PG195
Release Date
2025-11-20
Version
4.2 English

The ports in the following table appear at the boundary when the Internal Shared GT_COMMON and Clocking option is selected in the Shared Logic tab for 7 series Gen2 devices.

Table 1. Ports For Shared Logic (Internal Shared GT_COMMON and Clocking Option)
Name Direction Width
int_dclk_out O 1 bit
int_oobclk_out O 1 bit
int_pclk_sel_slave I 1 bit
int_pclk_out_slave O 1 bit
int_pipe_rxusrclk_out O 1 bit
int_qplllock_out O 2 bits
int_qplloutclk_out O 2 bits
int_qplloutrefclk_out O 2 bits
int_rxoutclk_out O 1 bit
int_userclk1_out O 1 bit
int_userclk2_out O 1 bit

The ports in the following table appear at the boundary when the Shared GT_COMMON option is selected in the Share Logic tab for 7 series Gen2 devices.

Table 2. Ports For Shared Logic (Shared GT_COMMON Option)
Name Direction Width
qpll_drp_crscode I 12 bits
qpll_drp_fsm I 18 bits
qpll_drp_done I 2 bits
qpll_drp_reset I 2 bits
qpll_qplllock I 2 bits
qpll_qplloutclk I 2 bits
qpll_qplloutrefclk I 2 bits
qpll_qplld O 1 bit
qpll_qpllreset O 2 bits
qpll_drp_clk O 1 bit
qpll_drp_rst_n O 1 bit
qpll_drp_ovrd O 1 bit
qpll_drp_gen3 O 1 bit
qpll_drp_start O 1 bit

The ports in the following table appear at the boundary when the Shared Clocking option is selected in the Share Logic tab for 7 series Gen2 devices.

Table 3. Ports For Shared Logic (Shared Clocking Option)
Name Direction Width
pipe_pclk_in I 1 bit
pipe_rxusrclk_in I 1 bit
pipe_rxoutclk_in I 1 bit
pipe_dclk_in I 1 bit
pipe_userclk1_in I 1 bit
pipe_userclk2_in I 1 bit
pipe_oobclk_in I 1 bit
pipe_mmcm_lock_in I 1 bit
pipe_mmcm_rst_n I 1 bit
pipe_txoutclk_out O 1 bit
pipe_rxoutclk_out O 1 bit
pipe_pclk_sel_out O 1 bit
pipe_gen3_out O 1 bit

The following table shows the new port added in this version of the IP. This port is available at the boundary when MSI-X feature is enabled and the device type is PCIe Endpoint.

Table 4. New Port
Name Direction Width
msix_en O 1 bit