Introduction - 4.2 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2025-05-29
Version
4.2 English

The AMD DMA/Bridge Subsystem for PCI Express® ( PCIe® ) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express 2.1, 3.x, and 4.0 Integrated Block. The IP provides a choice between an AXI4 Memory Mapped or AXI4-Stream user interface.

This IP optionally also supports a PCIe AXI Bridge mode which is enabled for only AMD UltraScale+™ and AMD Spartan™ UltraScale+™ devices. For details about PCIe AXI Bridge mode operation, see AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194).

This document covers DMA mode operation only.

Important: In this product guide, AMD UltraScale+™ refers to both the existing UltraScale+ and the new Spartan UltraScale+ devices.