IRQ Block User Vector Number (0x84) - 4.2 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document ID
PG195
Release Date
2025-05-29
Version
4.2 English

If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In legacy interrupts, only the 2 LSB of each field should be used to map to INTA, B, C, or D.

Table 1. IRQ Block User Vector Number (0x84)
Bit Index Default Access Type Description
28:24 5’h0 RW

vector 7

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[7].
20:16 5’h0 RW

vector 6

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[6].
12:8 5’h0 RW

vector 5

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[5].
4:0 5’h0 RW

vector 4

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[4].