IRQ Block User Interrupt Pending (0x48) - IRQ Block User Interrupt Pending (0x48) - v4.2 English

IRQ Block User Interrupt Pending (0x48) - IRQ Block User Interrupt Pending (0x48) - v4.2 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document_ID

PG195

Release_Date

2026-07-22

Version

v4.2 English

Table 1. IRQ Block User Interrupt Pending (0x48)
Bit Index	Default	Access Type	Description
[NUM_USR_INT-1:0]	‘h0	RO	user_int_pend User Interrupt Pending. This register indicates pending events. The pending events are cleared by removing the event cause condition at the source component.