H2C Channel Performance Cycle Count (0xC8) - 4.2 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2025-05-29
Version
4.2 English
Table 1. H2C Channel Performance Cycle Count (0xC8)
Bit Index Default Access Type Description
16 1’b0 RO

pmon_cyc_count_maxed

Cycle count maximum was hit.

9:0 10’h0 RO

pmon_cyc_count [41:32]

Increments once per clock while running. See the Performance Monitor Control register (0xC0) bits Clear and Auto for clearing.