AXI4 Memory Mapped Write Response Interface Signals - AXI4 Memory Mapped Write Response Interface Signals - v4.2 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document_ID
PG195
Release_Date
2026-07-22
Version
v4.2 English
Table 1. AXI4 Memory Mapped Write Response Interface Signals
Signal Name Direction Description
m_axi_bvalid I Master write response valid.
m_axi_bresp[1:0] I Master write response.

m_axi_bid

[ID_WIDTH-1:0]

 I Master response ID.
m_axi_bready O Master response ready.