For endpoint configurations, the sys_rst_n signal
should be driven by the
PCI Express®
edge connector
reset (perstn). This serves as the reset for the
PCI Express interface.
The axi_aresetn output the AXI reset signal synchronous with the clock provided
on the axi_aclk output. This reset should drive all corresponding AXI
Interconnect aresetn signals.
The following figure shows the Endpoint system reset connection for the core in an AMD UltraScale™ device.
The following figure shows the Endpoint system reset connection for the core in an UltraScale+ device.
For Root Port configurations, the sys_rst_n
signal is internally generated by the user design. This serves as the reset to the
PCI Express slot connector reset (perstn).
The following figure shows the Root Port system reset connection for the core in an UltraScale device.
The following figure shows the Root Port system reset connection for the core in an UltraScale+ device.
Available for the DMA/Bridge Subsystem for PCIe in AXI Bridge mode, there is an optional dma_bridge_resetn input pin which allows you to reset all internal Bridge
engines and registers as well as all AXI peripherals driven by axi_aresetn and axi_ctl_aresetn pins.
When the following parameter is set, dma_bridge_resetn
does not need to be asserted during initial link up operation because it will be done
automatically by the IP. You must terminate all transactions before asserting this pin.
After being asserted, the pin must be kept asserted for a minimum duration of at least
equal to the Completion Timeout value (typically 50 ms) to clear any pending transfer
that may currently be queued in the data path. To set this parameter, type the following
command at the Tcl command line:
set_property -dict [list CONFIG.soft_reset_en {true}] [get_ips <ip_name>]