The following figure shows the debug options, which enable you to use of the debug utilities of the AMD UltraScale™ and AMD Virtex™ 7 XT PCI Express® subcores.
Figure 1. Debug Options
- Enable JTAG Debugger
- When selected, the JTAG debugger option of the base IP is set to true which enables the debugging capability of the subcore through the JTAG interface. For more details, see Virtex 7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023), and UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156).
- Enable In System IBERT
- This debug option is used to view the eye diagram of the serial link at the desired link speed. This option is available for AMD UltraScale devices only, and not supported for AMD Virtex™ 7 XT devices. For more details, see UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156).
- Enable Descrambler for Gen3 Mode
- This debug option integrates an encrypted version of the descrambler module inside the PCIe core, which is used to descramble the PIPE data to/from the PCIe integrated block in Gen3 link speed mode. This provides hardware-only support to debug on the board.