A Completer Abort occurs when the completion TLP completion status is
0b100 - Completer Abort. This indicates that the
completer has encountered a state in which it was unable to complete the transaction.
When the slave bridge receives a completer abort response, the Slave Completer Abort
(SCA) interrupt is asserted and the SLVERR response is asserted with arbitrary data on
the memory mapped AXI4 bus.
| Transfer Type | Abnormal Condition | Bridge Response |
|---|---|---|
| Read | Illegal burst type |
SIB interrupt is asserted. SLVERR response given with arbitrary read data. |
| Write | Illegal burst type |
SIB interrupt is asserted. Write data is discarded. SLVERR response given. |
| Read | Unexpected completion |
SUC interrupt is asserted. Completion is discarded. |
| Read | Unsupported Request status returned |
SUR interrupt is asserted. DECERR response given with arbitrary read data. |
| Read | Completion timeout | For PCIe Memory Read request, AXI Bridge for PCIe Gen3 IP provides SLVERR response, while DMA/Bridge Subsystem for PCIe in Bridge Mode IP provides OKAY response with 0s data on the AXI4 memory mapped bus. |
| Read | Poison bit in completion |
Completion data is discarded. SEP interrupt is asserted. SLVERR response given with arbitrary read data. |
| Read | Completer Abort (CA) status returned |
SCA interrupt is asserted. SLVERR response given with arbitrary read data. |