AXI Bridge for PCIe Gen3 - AXI Bridge for PCIe Gen3 - 3.0 English - PG194

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document_ID
PG194
Release_Date
2025-11-20
Version
3.0 English

The Interrupts modes in the following section applies to AXI Bridge for PCIe Gen3 only. For DMA/Bridge Subsystem for PCIe in Bridge Mode, go to the next section.

Multiple interrupt modes can be configured during IP configuration, however only one interrupt mode is used at runtime. If multiple interrupt modes are enabled by the host after PCI bus enumeration at runtime, the core uses the MSI interrupt over Legacy interrupt. Both MSI and Legacy interrupt modes are sent using the same int_msi_* interface, and the core automatically picks the best available interrupt mode at runtime. MSI-X is implemented externally to the core and uses a separate cfg_interrupt_msix_* interface. The core does not prevent the use of MSI-X at any time even when other interrupt modes are enabled, however, AMD recommends the use of MSI-X interrupt solely if enabled over other interrupt modes even if they are all enabled at runtime.